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arm: dts: lx2160aqds: add nodes describing possible mezzanine cards
Add device trees describing possible uses of mezzanine cards depending on the SERDES protocol employed. This patch adds DPAA2 networking support for the following protocols on each SERDES block: * SD #1: 3, 7, 19, 20 * SD #2: 11 Each SERDES block has a different device tree file per protocol supported, where the IO SLOTs used are enabled and PHYs located on the mezzanine cards are described. Also, dpmac nodes are edited and their associated phy-connection-type and phy-handle are added. Top DTS files are also added for each combination of protocol on the 3 SERDES blocks. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Ioana Ciornei
Priyanka Jain
parent
3695e4ccfd
commit
74f04490f2
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@ -383,7 +383,15 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
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fsl-ls1028a-qds-duart.dtb \
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fsl-ls1028a-qds-lpuart.dtb \
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fsl-lx2160a-rdb.dtb \
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fsl-lx2160a-qds.dtb
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fsl-lx2160a-qds.dtb \
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fsl-lx2160a-qds-3-x-x.dtb \
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fsl-lx2160a-qds-3-11-x.dtb \
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fsl-lx2160a-qds-7-x-x.dtb \
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fsl-lx2160a-qds-7-11-x.dtb \
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fsl-lx2160a-qds-19-x-x.dtb \
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fsl-lx2160a-qds-19-11-x.dtb \
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fsl-lx2160a-qds-20-x-x.dtb \
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fsl-lx2160a-qds-20-11-x.dtb
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dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
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fsl-ls1043a-qds-lpuart.dtb \
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fsl-ls1043a-rdb.dtb \
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19
arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts
Normal file
19
arch/arm/dts/fsl-lx2160a-qds-19-11-x.dts
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@ -0,0 +1,19 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source for SERDES protocol 19.11.x
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*
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* Copyright 2020 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-lx2160a-qds-sd1-19.dtsi"
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#include "fsl-lx2160a-qds-sd2-11.dtsi"
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/ {
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model = "NXP Layerscape LX2160AQDS Board (DTS 19.11.x)";
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compatible = "fsl,lx2160aqds", "fsl,lx2160a";
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};
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17
arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts
Normal file
17
arch/arm/dts/fsl-lx2160a-qds-19-x-x.dts
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@ -0,0 +1,17 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source for SERDES protocol 19.x.x
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*
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* Copyright 2020 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-lx2160a-qds-sd1-19.dtsi"
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/ {
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model = "NXP Layerscape LX2160AQDS Board (DTS 19.x.x)";
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compatible = "fsl,lx2160aqds", "fsl,lx2160a";
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};
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19
arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts
Normal file
19
arch/arm/dts/fsl-lx2160a-qds-20-11-x.dts
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@ -0,0 +1,19 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source for SERDES protocol 20.11.x
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*
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* Copyright 2020 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-lx2160a-qds-sd1-20.dtsi"
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#include "fsl-lx2160a-qds-sd2-11.dtsi"
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/ {
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model = "NXP Layerscape LX2160AQDS Board (DTS 20.11.x)";
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compatible = "fsl,lx2160aqds", "fsl,lx2160a";
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};
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17
arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts
Normal file
17
arch/arm/dts/fsl-lx2160a-qds-20-x-x.dts
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@ -0,0 +1,17 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source for SERDES protocol 20.x.x
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*
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* Copyright 2020 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-lx2160a-qds-sd1-20.dtsi"
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/ {
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model = "NXP Layerscape LX2160AQDS Board (DTS 20.x.x)";
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compatible = "fsl,lx2160aqds", "fsl,lx2160a";
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};
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19
arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts
Normal file
19
arch/arm/dts/fsl-lx2160a-qds-3-11-x.dts
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@ -0,0 +1,19 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source for SERDES protocol 3.11.x
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*
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* Copyright 2020 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-lx2160a-qds-sd1-3.dtsi"
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#include "fsl-lx2160a-qds-sd2-11.dtsi"
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/ {
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model = "NXP Layerscape LX2160AQDS Board (DTS 3.11.x)";
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compatible = "fsl,lx2160aqds", "fsl,lx2160a";
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};
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17
arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts
Normal file
17
arch/arm/dts/fsl-lx2160a-qds-3-x-x.dts
Normal file
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@ -0,0 +1,17 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source for SERDES protocol 3.x.x
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*
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* Copyright 2020 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-lx2160a-qds-sd1-3.dtsi"
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/ {
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model = "NXP Layerscape LX2160AQDS Board (DTS 3.x.x)";
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compatible = "fsl,lx2160aqds", "fsl,lx2160a";
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};
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19
arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts
Normal file
19
arch/arm/dts/fsl-lx2160a-qds-7-11-x.dts
Normal file
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@ -0,0 +1,19 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source for SERDES protocol 7.11.x
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*
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* Copyright 2020 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-lx2160a-qds-sd1-7.dtsi"
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#include "fsl-lx2160a-qds-sd2-11.dtsi"
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/ {
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model = "NXP Layerscape LX2160AQDS Board (DTS 7.11.x)";
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compatible = "fsl,lx2160aqds", "fsl,lx2160a";
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};
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17
arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts
Normal file
17
arch/arm/dts/fsl-lx2160a-qds-7-x-x.dts
Normal file
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@ -0,0 +1,17 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source for SERDES protocol 7.x.x
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*
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* Copyright 2020 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-lx2160a-qds-sd1-7.dtsi"
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/ {
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model = "NXP Layerscape LX2160AQDS Board (DTS 7-x-x)";
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compatible = "fsl,lx2160aqds", "fsl,lx2160a";
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};
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75
arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi
Normal file
75
arch/arm/dts/fsl-lx2160a-qds-sd1-19.dtsi
Normal file
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@ -0,0 +1,75 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 19
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*
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* Some assumptions are made:
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* * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4)
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* * mezzanine card M13 is connected to IO SLOT6 (25g-aui for DPMAC 5,6)
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* * mezzanine card M7 is connected to IO SLOT2 (xlaui4 for DPMAC 2)
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*
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* Copyright 2020 NXP
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*
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*/
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#include "fsl-lx2160a-qds.dtsi"
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&dpmac2 {
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status = "okay";
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phy-handle = <&cortina_phy0>;
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phy-connection-type = "xlaui4";
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};
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&dpmac3 {
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status = "okay";
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phy-handle = <&aquantia_phy1>;
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phy-connection-type = "usxgmii";
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};
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&dpmac4 {
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status = "okay";
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phy-handle = <&aquantia_phy2>;
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phy-connection-type = "usxgmii";
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};
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&dpmac5 {
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status = "okay";
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phy-handle = <&inphi_phy0>;
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phy-connection-type = "25g-aui";
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};
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&dpmac6 {
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status = "okay";
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phy-handle = <&inphi_phy1>;
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phy-connection-type = "25g-aui";
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};
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&emdio1_slot1 {
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aquantia_phy1: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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aquantia_phy2: ethernet-phy@5 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x1>;
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};
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};
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&emdio1_slot2 {
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cortina_phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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};
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&emdio1_slot6 {
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inphi_phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id0210.7440";
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reg = <0x0>;
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};
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inphi_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-id0210.7440";
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reg = <0x1>;
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};
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};
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39
arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi
Normal file
39
arch/arm/dts/fsl-lx2160a-qds-sd1-20.dtsi
Normal file
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@ -0,0 +1,39 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 20
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*
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* Some assumptions are made:
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* * 2 mezzanine cards M13 are connected to IO SLOT1 and IO SLOT2
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* (xlaui4 for DPMAC 1,2)
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*
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* Copyright 2020 NXP
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*
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*/
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#include "fsl-lx2160a-qds.dtsi"
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&dpmac1 {
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status = "okay";
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phy-handle = <&cortina_phy1_0>;
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phy-connection-type = "xlaui4";
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};
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&dpmac2 {
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status = "okay";
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phy-handle = <&cortina_phy2_0>;
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phy-connection-type = "xlaui4";
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};
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&emdio1_slot1 {
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cortina_phy1_0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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};
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&emdio1_slot2 {
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cortina_phy2_0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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};
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55
arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi
Normal file
55
arch/arm/dts/fsl-lx2160a-qds-sd1-3.dtsi
Normal file
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@ -0,0 +1,55 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 3
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*
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* Some assumptions are made:
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* * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6)
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*
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* Copyright 2020 NXP
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*
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*/
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#include "fsl-lx2160a-qds.dtsi"
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&dpmac3 {
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status = "okay";
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phy-handle = <&aquantia_phy1>;
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phy-connection-type = "usxgmii";
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};
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&dpmac4 {
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status = "okay";
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phy-handle = <&aquantia_phy2>;
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phy-connection-type = "usxgmii";
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};
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&dpmac5 {
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status = "okay";
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phy-handle = <&aquantia_phy3>;
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phy-connection-type = "usxgmii";
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};
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&dpmac6 {
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status = "okay";
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phy-handle = <&aquantia_phy4>;
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phy-connection-type = "usxgmii";
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};
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&emdio1_slot1 {
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aquantia_phy1: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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aquantia_phy2: ethernet-phy@5 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x1>;
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};
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aquantia_phy3: ethernet-phy@6 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x2>;
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};
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aquantia_phy4: ethernet-phy@7 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x3>;
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};
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};
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100
arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi
Normal file
100
arch/arm/dts/fsl-lx2160a-qds-sd1-7.dtsi
Normal file
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@ -0,0 +1,100 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 7
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*
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* Some assumptions are made:
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* * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4,5,6)
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* * mezzanine card M1/M4 is connected to IO SLOT2 (sgmii for DPMAC 7,8,9,10)
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*
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* Copyright 2020 NXP
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*
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*/
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#include "fsl-lx2160a-qds.dtsi"
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&dpmac3 {
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status = "okay";
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phy-handle = <&aquantia_phy1>;
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phy-connection-type = "usxgmii";
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};
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&dpmac4 {
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status = "okay";
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phy-handle = <&aquantia_phy2>;
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phy-connection-type = "usxgmii";
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};
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&dpmac5 {
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status = "okay";
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phy-handle = <&aquantia_phy3>;
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phy-connection-type = "usxgmii";
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};
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&dpmac6 {
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status = "okay";
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phy-handle = <&aquantia_phy4>;
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phy-connection-type = "usxgmii";
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};
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&dpmac7 {
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status = "okay";
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phy-handle = <&sgmii_phy1>;
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phy-connection-type = "sgmii";
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};
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&dpmac8 {
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status = "okay";
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phy-handle = <&sgmii_phy2>;
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phy-connection-type = "sgmii";
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};
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&dpmac9 {
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status = "okay";
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phy-handle = <&sgmii_phy3>;
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phy-connection-type = "sgmii";
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};
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&dpmac10 {
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status = "okay";
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phy-handle = <&sgmii_phy4>;
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phy-connection-type = "sgmii";
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};
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&emdio1_slot1 {
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aquantia_phy1: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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aquantia_phy2: ethernet-phy@5 {
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compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x1>;
|
||||
};
|
||||
|
||||
aquantia_phy3: ethernet-phy@6 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
aquantia_phy4: ethernet-phy@7 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <0x3>;
|
||||
};
|
||||
};
|
||||
|
||||
&emdio1_slot2 {
|
||||
sgmii_phy1: ethernet-phy@1c {
|
||||
reg = <0x1c>;
|
||||
};
|
||||
|
||||
sgmii_phy2: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
sgmii_phy3: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
sgmii_phy4: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
76
arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi
Normal file
76
arch/arm/dts/fsl-lx2160a-qds-sd2-11.dtsi
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* NXP LX2160AQDS device tree source for the SERDES block #2 - protocol 11
|
||||
*
|
||||
* Some assumptions are made:
|
||||
* * 2 mezzanine cards M1/M4 are connected to IO SLOT 7 and IO SLOT 8
|
||||
* (sgmii for DPMAC 12, 13, 14, 16, 17, 18)
|
||||
*
|
||||
* Copyright 2020 NXP
|
||||
*
|
||||
*/
|
||||
#include "fsl-lx2160a-qds.dtsi"
|
||||
|
||||
&dpmac12 {
|
||||
status = "okay";
|
||||
phy-handle = <&sgmii_phy7_2>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
&dpmac17 {
|
||||
status = "okay";
|
||||
phy-handle = <&sgmii_phy7_3>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
&dpmac18 {
|
||||
status = "okay";
|
||||
phy-handle = <&sgmii_phy7_4>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
&dpmac16 {
|
||||
status = "okay";
|
||||
phy-handle = <&sgmii_phy8_2>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
&dpmac13 {
|
||||
status = "okay";
|
||||
phy-handle = <&sgmii_phy8_3>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
&dpmac14 {
|
||||
status = "okay";
|
||||
phy-handle = <&sgmii_phy8_4>;
|
||||
phy-connection-type = "sgmii";
|
||||
};
|
||||
|
||||
&emdio1_slot7 {
|
||||
sgmii_phy7_2: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
sgmii_phy7_3: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
sgmii_phy7_4: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
||||
&emdio1_slot8 {
|
||||
sgmii_phy8_2: ethernet-phy@1d {
|
||||
reg = <0x1d>;
|
||||
};
|
||||
|
||||
sgmii_phy8_3: ethernet-phy@1e {
|
||||
reg = <0x1e>;
|
||||
};
|
||||
|
||||
sgmii_phy8_4: ethernet-phy@1f {
|
||||
reg = <0x1f>;
|
||||
};
|
||||
};
|
||||
|
|
@ -1,14 +1,14 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* NXP LX2160AQDS device tree source
|
||||
* NXP LX2160AQDS default device tree source
|
||||
*
|
||||
* Copyright 2018-2020 NXP
|
||||
* Copyright 2020 NXP
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "fsl-lx2160a.dtsi"
|
||||
#include "fsl-lx2160a-qds.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NXP Layerscape LX2160AQDS Board";
|
||||
|
|
@ -17,177 +17,3 @@
|
|||
spi0 = &fspi;
|
||||
};
|
||||
};
|
||||
|
||||
&dpmac17 {
|
||||
status = "okay";
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
&dpmac18 {
|
||||
status = "okay";
|
||||
phy-handle = <&rgmii_phy2>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
&emdio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&emdio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
fpga@66 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "simple-mfd";
|
||||
reg = <0x66>;
|
||||
|
||||
mux-mdio@54 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mdio-mux-i2creg";
|
||||
reg = <0x54>;
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
|
||||
mdio-parent-bus = <&emdio1>;
|
||||
|
||||
mdio@00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x00>;
|
||||
|
||||
rgmii_phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
mdio@08 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40>;
|
||||
|
||||
rgmii_phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
emdio1_slot1: mdio@c0 { /* I/O Slot #1 */
|
||||
reg = <0xC0>;
|
||||
device-name = "emdio1_slot1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emdio1_slot2: mdio@c8 { /* I/O Slot #2 */
|
||||
reg = <0xC8>;
|
||||
device-name = "emdio1_slot2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emdio1_slot3: mdio@d0 { /* I/O Slot #3 */
|
||||
reg = <0xD0>;
|
||||
device-name = "emdio1_slot3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emdio1_slot4: mdio@d8 { /* I/O Slot #4 */
|
||||
reg = <0xD8>;
|
||||
device-name = "emdio1_slot4";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emdio1_slot5: mdio@e0 { /* I/O Slot #5 */
|
||||
reg = <0xE0>;
|
||||
device-name = "emdio1_slot5";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emdio1_slot6: mdio@e8 { /* I/O Slot #6 */
|
||||
reg = <0xE8>;
|
||||
device-name = "emdio1_slot6";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emdio1_slot7: mdio@f0 { /* I/O Slot #7 */
|
||||
reg = <0xF0>;
|
||||
device-name = "emdio1_slot7";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emdio1_slot8: mdio@f8 { /* I/O Slot #8 */
|
||||
reg = <0xF8>;
|
||||
device-name = "emdio1_slot8";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
i2c-mux@77 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x77>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3>;
|
||||
|
||||
rtc@51 {
|
||||
compatible = "pcf2127-rtc";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fspi {
|
||||
status = "okay";
|
||||
|
||||
mt35xu512aba0: flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
spi-rx-bus-width = <8>;
|
||||
spi-tx-bus-width = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
169
arch/arm/dts/fsl-lx2160a-qds.dtsi
Normal file
169
arch/arm/dts/fsl-lx2160a-qds.dtsi
Normal file
|
|
@ -0,0 +1,169 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+ OR X11
|
||||
/*
|
||||
* NXP LX2160AQDS common device tree source
|
||||
*
|
||||
* Copyright 2018-2019 NXP
|
||||
*
|
||||
*/
|
||||
|
||||
#include "fsl-lx2160a.dtsi"
|
||||
|
||||
&dpmac17 {
|
||||
status = "okay";
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
&dpmac18 {
|
||||
status = "okay";
|
||||
phy-handle = <&rgmii_phy2>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
&emdio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&emdio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
fpga@66 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "simple-mfd";
|
||||
reg = <0x66>;
|
||||
|
||||
mux-mdio@54 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "mdio-mux-i2creg";
|
||||
reg = <0x54>;
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x54 0xf8>; // reg 0x54, bits 7:3
|
||||
mdio-parent-bus = <&emdio1>;
|
||||
|
||||
mdio@00 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x00>;
|
||||
|
||||
rgmii_phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
};
|
||||
};
|
||||
mdio@08 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40>;
|
||||
|
||||
rgmii_phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
};
|
||||
|
||||
emdio1_slot1: mdio@c0 { /* I/O Slot #1 */
|
||||
reg = <0xC0>;
|
||||
device-name = "emdio1_slot1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emdio1_slot2: mdio@c8 { /* I/O Slot #2 */
|
||||
reg = <0xC8>;
|
||||
device-name = "emdio1_slot2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emdio1_slot3: mdio@d0 { /* I/O Slot #3 */
|
||||
reg = <0xD0>;
|
||||
device-name = "emdio1_slot3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emdio1_slot4: mdio@d8 { /* I/O Slot #4 */
|
||||
reg = <0xD8>;
|
||||
device-name = "emdio1_slot4";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emdio1_slot5: mdio@e0 { /* I/O Slot #5 */
|
||||
reg = <0xE0>;
|
||||
device-name = "emdio1_slot5";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emdio1_slot6: mdio@e8 { /* I/O Slot #6 */
|
||||
reg = <0xE8>;
|
||||
device-name = "emdio1_slot6";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emdio1_slot7: mdio@f0 { /* I/O Slot #7 */
|
||||
reg = <0xF0>;
|
||||
device-name = "emdio1_slot7";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
emdio1_slot8: mdio@f8 { /* I/O Slot #8 */
|
||||
reg = <0xF8>;
|
||||
device-name = "emdio1_slot8";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
i2c-mux@77 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x77>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x3>;
|
||||
|
||||
rtc@51 {
|
||||
compatible = "pcf2127-rtc";
|
||||
reg = <0x51>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sata0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata3 {
|
||||
status = "okay";
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user