u-boot-brain/arch/riscv/cpu/ax25/Kconfig
Rick Chen a8323d1816 riscv: ax25: add imply v5l2 cache controller
Select the v5l2 UCLASS_CACHE driver for ax25.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03 09:31:03 +08:00

23 lines
581 B
Plaintext

config RISCV_NDS
bool
select ARCH_EARLY_INIT_R
imply CPU
imply CPU_RISCV
imply RISCV_TIMER
imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
imply V5L2_CACHE
help
Run U-Boot on AndeStar V5 platforms and use some specific features
which are provided by Andes Technology AndeStar V5 families.
if RISCV_NDS
config RISCV_NDS_CACHE
bool "AndeStar V5 families specific cache support"
depends on RISCV_MMODE || SPL_RISCV_MMODE
help
Provide Andes Technology AndeStar V5 families specific cache support.
endif