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riscv: ax25: add imply v5l2 cache controller

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Select the v5l2 UCLASS_CACHE driver for ax25.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Rick Chen 2019-08-29 10:30:13 +08:00 committed by Andes
parent edf0acb3b4
commit a8323d1816
1 changed files with 1 additions and 0 deletions
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arch/riscv/cpu/ax25/Kconfig
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@ -6,6 +6,7 @@ config RISCV_NDS
imply RISCV_TIMER
imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
imply V5L2_CACHE
help
Run U-Boot on AndeStar V5 platforms and use some specific features
which are provided by Andes Technology AndeStar V5 families.