mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
cb753850e8
Updated the RCW for rev2.0 which uses new frequency settings as below: Clock Configuration: CPU0:1666.667 MHz, CPU1:1666.667 MHz, CPU2:1666.667 MHz, CPU3:1666.667 MHz, CPU4:1666.667 MHz, CPU5:1666.667 MHz, CPU6:1666.667 MHz, CPU7:1666.667 MHz, CPU8:1666.667 MHz, CPU9:1666.667 MHz, CPU10:1666.667 MHz, CPU11:1666.667MHz, CCB:733.333 MHz, DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:183.333 MHz FMAN1: 733.333 MHz FMAN2: 733.333 MHz QMAN: 366.667 MHz PME: 533.333 MHz Remove workaround of IFC bus speed and SERDES A-006031 of rev1.0. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
23 lines
393 B
INI
23 lines
393 B
INI
#PBI commands
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#Initialize CPC1
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09010000 00200400
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09138000 00000000
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091380c0 00000100
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#512KB SRAM
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09010100 00000000
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09010104 fff80009
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09010f00 08000000
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#enable CPC1
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09010000 80000000
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#Configure LAW for CPC1
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09000d00 00000000
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09000d04 fff80000
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09000d08 81000012
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#Configure alternate space
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09000010 00000000
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09000014 ff000000
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09000018 81000000
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#Flush PBL data
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09138000 00000000
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091380c0 00000000
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