mirror of
https://github.com/brain-hackers/u-boot-brain
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c2a61cd232
Some Freescale SoCs like T1020 and T1040 have an integrated L2 Switch. The L2 Switch ports may be connected to Ethernet PHYs over SGMII and QSGMII. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
384 lines
11 KiB
C
384 lines
11 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/fsl_serdes.h>
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#include <asm/immap_85xx.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/fsl_law.h>
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#include <asm/errno.h>
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#include <asm/fsl_errata.h>
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#include "fsl_corenet2_serdes.h"
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#ifdef CONFIG_SYS_FSL_SRDS_1
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static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_3
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static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_4
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static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
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#endif
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#ifdef DEBUG
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static const char *serdes_prtcl_str[] = {
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[NONE] = "NA",
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[PCIE1] = "PCIE1",
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[PCIE2] = "PCIE2",
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[PCIE3] = "PCIE3",
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[PCIE4] = "PCIE4",
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[SATA1] = "SATA1",
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[SATA2] = "SATA2",
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[SRIO1] = "SRIO1",
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[SRIO2] = "SRIO2",
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[SGMII_FM1_DTSEC1] = "SGMII_FM1_DTSEC1",
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[SGMII_FM1_DTSEC2] = "SGMII_FM1_DTSEC2",
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[SGMII_FM1_DTSEC3] = "SGMII_FM1_DTSEC3",
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[SGMII_FM1_DTSEC4] = "SGMII_FM1_DTSEC4",
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[SGMII_FM1_DTSEC5] = "SGMII_FM1_DTSEC5",
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[SGMII_FM1_DTSEC6] = "SGMII_FM1_DTSEC6",
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[SGMII_FM2_DTSEC1] = "SGMII_FM2_DTSEC1",
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[SGMII_FM2_DTSEC2] = "SGMII_FM2_DTSEC2",
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[SGMII_FM2_DTSEC3] = "SGMII_FM2_DTSEC3",
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[SGMII_FM2_DTSEC4] = "SGMII_FM2_DTSEC4",
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[XAUI_FM1] = "XAUI_FM1",
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[XAUI_FM2] = "XAUI_FM2",
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[AURORA] = "DEBUG",
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[CPRI1] = "CPRI1",
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[CPRI2] = "CPRI2",
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[CPRI3] = "CPRI3",
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[CPRI4] = "CPRI4",
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[CPRI5] = "CPRI5",
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[CPRI6] = "CPRI6",
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[CPRI7] = "CPRI7",
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[CPRI8] = "CPRI8",
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[XAUI_FM1_MAC9] = "XAUI_FM1_MAC9",
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[XAUI_FM1_MAC10] = "XAUI_FM1_MAC10",
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[XAUI_FM2_MAC9] = "XAUI_FM2_MAC9",
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[XAUI_FM2_MAC10] = "XAUI_FM2_MAC10",
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[HIGIG_FM1_MAC9] = "HiGig_FM1_MAC9",
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[HIGIG_FM1_MAC10] = "HiGig_FM1_MAC10",
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[HIGIG_FM2_MAC9] = "HiGig_FM2_MAC9",
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[HIGIG_FM2_MAC10] = "HiGig_FM2_MAC10",
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[QSGMII_FM1_A] = "QSGMII_FM1_A",
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[QSGMII_FM1_B] = "QSGMII_FM1_B",
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[QSGMII_FM2_A] = "QSGMII_FM2_A",
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[QSGMII_FM2_B] = "QSGMII_FM2_B",
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[XFI_FM1_MAC9] = "XFI_FM1_MAC9",
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[XFI_FM1_MAC10] = "XFI_FM1_MAC10",
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[XFI_FM2_MAC9] = "XFI_FM2_MAC9",
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[XFI_FM2_MAC10] = "XFI_FM2_MAC10",
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[INTERLAKEN] = "INTERLAKEN",
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[QSGMII_SW1_A] = "QSGMII_SW1_A",
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[QSGMII_SW1_B] = "QSGMII_SW1_B",
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[SGMII_SW1_MAC1] = "SGMII_SW1_MAC1",
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[SGMII_SW1_MAC2] = "SGMII_SW1_MAC2",
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[SGMII_SW1_MAC3] = "SGMII_SW1_MAC3",
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[SGMII_SW1_MAC4] = "SGMII_SW1_MAC4",
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[SGMII_SW1_MAC5] = "SGMII_SW1_MAC5",
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[SGMII_SW1_MAC6] = "SGMII_SW1_MAC6",
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};
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#endif
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int is_serdes_configured(enum srds_prtcl device)
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{
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int ret = 0;
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#ifdef CONFIG_SYS_FSL_SRDS_1
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ret |= serdes1_prtcl_map[device];
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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ret |= serdes2_prtcl_map[device];
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_3
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ret |= serdes3_prtcl_map[device];
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_4
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ret |= serdes4_prtcl_map[device];
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#endif
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return !!ret;
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}
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int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
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{
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const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 cfg = in_be32(&gur->rcwsr[4]);
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int i;
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switch (sd) {
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#ifdef CONFIG_SYS_FSL_SRDS_1
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case FSL_SRDS_1:
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cfg &= FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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cfg >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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break;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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case FSL_SRDS_2:
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cfg &= FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
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cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
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break;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_3
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case FSL_SRDS_3:
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cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
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cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
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break;
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_4
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case FSL_SRDS_4:
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cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
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cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
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break;
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#endif
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default:
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printf("invalid SerDes%d\n", sd);
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break;
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}
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/* Is serdes enabled at all? */
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if (unlikely(cfg == 0))
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return -ENODEV;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (serdes_get_prtcl(sd, cfg, i) == device)
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return i;
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}
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return -ENODEV;
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}
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#define BC3_SHIFT 9
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#define DC3_SHIFT 6
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#define FC3_SHIFT 0
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#define BC2_SHIFT 19
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#define DC2_SHIFT 16
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#define FC2_SHIFT 10
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#define BC1_SHIFT 29
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#define DC1_SHIFT 26
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#define FC1_SHIFT 20
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#define BC_MASK 0x1
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#define DC_MASK 0x7
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#define FC_MASK 0x3F
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#define FUSE_VAL_MASK 0x00000003
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#define FUSE_VAL_SHIFT 30
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#define CR0_DCBIAS_SHIFT 5
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#define CR1_FCAP_SHIFT 15
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#define CR1_BCAP_SHIFT 29
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#define FCAP_MASK 0x001F8000
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#define BCAP_MASK 0x20000000
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#define BCAP_OVD_MASK 0x10000000
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#define BYP_CAL_MASK 0x02000000
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void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
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u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
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{
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ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 cfg;
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int lane;
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memset(serdes_prtcl_map, 0, sizeof(serdes_prtcl_map));
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#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
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struct ccsr_sfp_regs __iomem *sfp_regs =
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(struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
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u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
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u32 bc_status, fc_status, dc_status, pll_sr2;
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serdes_corenet_t __iomem *srds_regs = (void *)sd_addr;
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u32 sfp_spfr0, sel;
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#endif
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cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
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/* Erratum A-007186
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* Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
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* The workaround requires factory pre-set SerDes calibration values to be
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* read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0)
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* These values have been shown to work across the
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* entire temperature range for all SerDes. These values are then written into
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* the SerDes registers to calibrate the SerDes PLL.
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*
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* This workaround for the protocols and rates that only have the Ring VCO.
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*/
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#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
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sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
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debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
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sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
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if (has_erratum_a007186() && (sel == 0x01 || sel == 0x02)) {
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for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
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pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
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debug("A007186: pll_num=%x pllcr0=%x\n",
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pll_num, pll_status);
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/* STEP 1 */
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/* Read factory pre-set SerDes calibration values
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* from fuse block(SFP scratch register-sfp_spfr0)
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*/
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switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
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case SRDS_PLLCR0_FRATE_SEL_3_0:
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case SRDS_PLLCR0_FRATE_SEL_3_072:
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debug("A007186: 3.0/3.072 protocol rate\n");
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bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
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dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
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fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
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break;
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case SRDS_PLLCR0_FRATE_SEL_3_125:
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debug("A007186: 3.125 protocol rate\n");
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bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
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dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
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fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
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break;
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case SRDS_PLLCR0_FRATE_SEL_3_75:
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debug("A007186: 3.75 protocol rate\n");
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bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
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dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
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fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
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break;
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default:
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continue;
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}
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/* STEP 2 */
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/* Write SRDSxPLLnCR1[11:16] = FC
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* Write SRDSxPLLnCR1[2] = BC
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*/
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pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
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pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) |
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((fc << CR1_FCAP_SHIFT) & FCAP_MASK));
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out_be32(&srds_regs->bank[pll_num].pllcr1,
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(pll_cr_upd | pll_cr1));
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debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
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pll_num, (pll_cr_upd | pll_cr1));
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/* Write SRDSxPLLnCR0[24:26] = DC
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*/
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pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
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out_be32(&srds_regs->bank[pll_num].pllcr0,
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pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
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debug("A007186: pll_num=%x, Updated PLLCR0=%x\n",
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pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
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/* Write SRDSxPLLnCR1[3] = 1
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* Write SRDSxPLLnCR1[6] = 1
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*/
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pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
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pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
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out_be32(&srds_regs->bank[pll_num].pllcr1,
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(pll_cr_upd | pll_cr1));
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debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
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pll_num, (pll_cr_upd | pll_cr1));
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/* STEP 3 */
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/* Read the status Registers */
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/* Verify SRDSxPLLnSR2[8] = BC */
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pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
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debug("A007186: pll_num=%x pllsr2=%x\n",
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pll_num, pll_sr2);
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bc_status = (pll_sr2 >> 23) & BC_MASK;
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if (bc_status != bc)
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debug("BC mismatch\n");
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fc_status = (pll_sr2 >> 16) & FC_MASK;
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if (fc_status != fc)
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debug("FC mismatch\n");
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pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
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out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 |
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0x02000000);
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pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
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dc_status = (pll_sr2 >> 17) & DC_MASK;
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if (dc_status != dc)
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debug("DC mismatch\n");
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pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
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out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 &
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0xfdffffff);
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/* STEP 4 */
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/* Wait 750us to verify the PLL is locked
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* by checking SRDSxPLLnCR0[8] = 1.
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*/
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udelay(750);
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pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
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debug("A007186: pll_num=%x pllcr0=%x\n",
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pll_num, pll_status);
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if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
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printf("A007186 Serdes PLL not locked\n");
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else
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debug("A007186 Serdes PLL locked\n");
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}
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}
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#endif
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cfg >>= sd_prctl_shift;
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printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
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if (!is_serdes_prtcl_valid(sd, cfg))
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printf("SERDES%d[PRTCL] = 0x%x is not valid\n", sd + 1, cfg);
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for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes_get_prtcl(sd, cfg, lane);
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if (unlikely(lane_prtcl >= SERDES_PRCTL_COUNT))
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debug("Unknown SerDes lane protocol %d\n", lane_prtcl);
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else
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serdes_prtcl_map[lane_prtcl] = 1;
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}
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}
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void fsl_serdes_init(void)
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{
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#ifdef CONFIG_SYS_FSL_SRDS_1
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serdes_init(FSL_SRDS_1,
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CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
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serdes1_prtcl_map);
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_2
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serdes_init(FSL_SRDS_2,
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CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
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FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
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FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
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serdes2_prtcl_map);
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_3
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serdes_init(FSL_SRDS_3,
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CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
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FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
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FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
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serdes3_prtcl_map);
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#endif
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#ifdef CONFIG_SYS_FSL_SRDS_4
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serdes_init(FSL_SRDS_4,
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CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
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FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
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FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
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serdes4_prtcl_map);
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#endif
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}
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const char *serdes_clock_to_string(u32 clock)
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{
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switch (clock) {
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case SRDS_PLLCR0_RFCK_SEL_100:
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return "100";
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case SRDS_PLLCR0_RFCK_SEL_125:
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return "125";
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case SRDS_PLLCR0_RFCK_SEL_156_25:
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return "156.25";
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case SRDS_PLLCR0_RFCK_SEL_161_13:
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return "161.1328123";
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default:
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#if defined(CONFIG_T4240QDS)
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return "???";
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#else
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return "122.88";
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#endif
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}
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}
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