arch/powerpc: Add SGMII support for the L2 Switch ports

Some Freescale SoCs like T1020 and T1040 have an integrated
L2 Switch. The L2 Switch ports may be connected to Ethernet PHYs
over SGMII and QSGMII.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Codrin Ciubotariu 2015-01-12 14:08:31 +02:00 committed by York Sun
parent 7d33a87d9d
commit c2a61cd232
3 changed files with 16 additions and 4 deletions

View File

@ -78,6 +78,12 @@ static const char *serdes_prtcl_str[] = {
[INTERLAKEN] = "INTERLAKEN",
[QSGMII_SW1_A] = "QSGMII_SW1_A",
[QSGMII_SW1_B] = "QSGMII_SW1_B",
[SGMII_SW1_MAC1] = "SGMII_SW1_MAC1",
[SGMII_SW1_MAC2] = "SGMII_SW1_MAC2",
[SGMII_SW1_MAC3] = "SGMII_SW1_MAC3",
[SGMII_SW1_MAC4] = "SGMII_SW1_MAC4",
[SGMII_SW1_MAC5] = "SGMII_SW1_MAC5",
[SGMII_SW1_MAC6] = "SGMII_SW1_MAC6",
};
#endif

View File

@ -33,10 +33,10 @@ static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
PCIE2, PCIE2, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0x87] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE2, PCIE3, PCIE4, SGMII_FM1_DTSEC5},
[0x89] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
PCIE2, PCIE3, QSGMII_SW1_B, SATA1},
[0x8D] = {PCIE1, QSGMII_SW1_A, QSGMII_SW1_A, QSGMII_SW1_A,
PCIE2, QSGMII_SW1_B, QSGMII_SW1_B, QSGMII_SW1_B},
[0x89] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
PCIE2, PCIE3, SGMII_SW1_MAC4, SATA1},
[0x8D] = {PCIE1, SGMII_SW1_MAC3, SGMII_SW1_MAC1, SGMII_SW1_MAC2,
PCIE2, SGMII_SW1_MAC6, SGMII_SW1_MAC4, SGMII_SW1_MAC5},
[0x8F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, NONE, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5},
[0xA5] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,

View File

@ -87,6 +87,12 @@ enum srds_prtcl {
SGMII_2500_FM2_DTSEC6,
SGMII_2500_FM2_DTSEC9,
SGMII_2500_FM2_DTSEC10,
SGMII_SW1_MAC1,
SGMII_SW1_MAC2,
SGMII_SW1_MAC3,
SGMII_SW1_MAC4,
SGMII_SW1_MAC5,
SGMII_SW1_MAC6,
SERDES_PRCTL_COUNT /* Keep this item the last one */
};