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https://github.com/brain-hackers/u-boot-brain
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ba932bc846
Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
108 lines
2.8 KiB
ArmAsm
108 lines
2.8 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017 Renesas Electronics
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* Copyright (C) 2017 Chris Brandt
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/macro.h>
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/* Watchdog Registers */
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#define RZA1_WDT_BASE 0xFCFE0000
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#define WTCSR (RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */
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#define WTCNT (RZA1_WDT_BASE + 0x02) /* Watchdog Timer Counter Register */
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#define WRCSR (RZA1_WDT_BASE + 0x04) /* Watchdog Reset Control Register */
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/* Standby controller registers (chapter 55) */
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#define RZA1_STBCR_BASE 0xFCFE0020
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#define STBCR1 (RZA1_STBCR_BASE + 0x00)
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#define STBCR2 (RZA1_STBCR_BASE + 0x04)
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#define STBCR3 (RZA1_STBCR_BASE + 0x400)
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#define STBCR4 (RZA1_STBCR_BASE + 0x404)
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#define STBCR5 (RZA1_STBCR_BASE + 0x408)
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#define STBCR6 (RZA1_STBCR_BASE + 0x40c)
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#define STBCR7 (RZA1_STBCR_BASE + 0x410)
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#define STBCR8 (RZA1_STBCR_BASE + 0x414)
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#define STBCR9 (RZA1_STBCR_BASE + 0x418)
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#define STBCR10 (RZA1_STBCR_BASE + 0x41c)
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#define STBCR11 (RZA1_STBCR_BASE + 0x420)
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#define STBCR12 (RZA1_STBCR_BASE + 0x424)
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#define STBCR13 (RZA1_STBCR_BASE + 0x450)
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/* Clock Registers */
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#define RZA1_FRQCR_BASE 0xFCFE0010
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#define FRQCR (RZA1_FRQCR_BASE + 0x00)
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#define FRQCR2 (RZA1_FRQCR_BASE + 0x04)
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#define SYSCR1 0xFCFE0400 /* System control register 1 */
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#define SYSCR2 0xFCFE0404 /* System control register 2 */
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#define SYSCR3 0xFCFE0408 /* System control register 3 */
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/* Disable WDT */
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#define WTCSR_D 0xA518
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#define WTCNT_D 0x5A00
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/* Enable all peripheral clocks */
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#define STBCR3_D 0x00000000
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#define STBCR4_D 0x00000000
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#define STBCR5_D 0x00000000
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#define STBCR6_D 0x00000000
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#define STBCR7_D 0x00000024
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#define STBCR8_D 0x00000005
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#define STBCR9_D 0x00000000
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#define STBCR10_D 0x00000000
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#define STBCR11_D 0x000000c0
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#define STBCR12_D 0x000000f0
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/*
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* Set all system clocks to full speed.
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* On reset, the CPU will be running at 1/2 speed.
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* In the Hardware Manual, see Table 6.3 Settable Frequency Ranges
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*/
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#define FRQCR_D 0x0035
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#define FRQCR2_D 0x0001
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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/* PL310 init */
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write32 0x3fffff80, 0x00000001
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/* Disable WDT */
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write16 WTCSR, WTCSR_D
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write16 WTCNT, WTCNT_D
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/* Set clocks */
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write16 FRQCR, FRQCR_D
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write16 FRQCR2, FRQCR2_D
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/* Enable all peripherals(Standby Control) */
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write8 STBCR3, STBCR3_D
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write8 STBCR4, STBCR4_D
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write8 STBCR5, STBCR5_D
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write8 STBCR6, STBCR6_D
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write8 STBCR7, STBCR7_D
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write8 STBCR8, STBCR8_D
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write8 STBCR9, STBCR9_D
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write8 STBCR10, STBCR10_D
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write8 STBCR11, STBCR11_D
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write8 STBCR12, STBCR12_D
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/* For serial booting, enable read ahead caching to speed things up */
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#define DRCR_0 0x3FEFA00C
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write32 DRCR_0, 0x00010100 /* Read Burst ON, Length=2 */
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/* Enable all internal RAM */
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write8 SYSCR1, 0xFF
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write8 SYSCR2, 0xFF
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write8 SYSCR3, 0xFF
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nop
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/* back to arch calling code */
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mov pc, lr
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.align 4
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