ARM: dts: renesas: Add RZ/A1 GR-Peach board
Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Chris Brandt
Marek Vasut
parent
3529596442
commit
ba932bc846
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@ -603,6 +603,9 @@ dtb-$(CONFIG_RCAR_GEN3) += \
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r8a77990-ebisu-u-boot.dtb \
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r8a77995-draak-u-boot.dtb
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dtb-$(CONFIG_RZA1) += \
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r7s72100-gr-peach-u-boot.dtb
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dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
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keystone-k2l-evm.dtb \
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keystone-k2e-evm.dtb \
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@ -0,0 +1,78 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source extras for U-Boot for the GR Peach board
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*
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* Copyright (C) 2019 Marek Vasut <marek.vasut@gmail.com>
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*/
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#include "r7s72100-gr-peach.dts"
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/ {
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aliases {
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spi0 = &rpc;
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};
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soc {
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u-boot,dm-pre-reloc;
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};
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leds {
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led1 {
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label = "peach:bottom:red";
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};
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led-red {
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label = "peach:tri:red";
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gpios = <&port6 13 GPIO_ACTIVE_HIGH>;
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};
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led-green {
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label = "peach:tri:green";
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gpios = <&port6 14 GPIO_ACTIVE_HIGH>;
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};
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led-blue {
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label = "peach:tri:blue";
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gpios = <&port6 15 GPIO_ACTIVE_HIGH>;
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};
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};
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rpc: rpc@0xee200000 {
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compatible = "renesas,rpc-r7s72100", "renesas,rpc";
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reg = <0x3fefa000 0x100>, <0x18000000 0x08000000>;
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bank-width = <2>;
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num-cs = <1>;
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status = "okay";
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spi-max-frequency = <50000000>;
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#address-cells = <1>;
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#size-cells = <0>;
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flash0: spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <1>;
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reg = <0>;
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status = "okay";
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};
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};
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};
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&ostm0 {
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u-boot,dm-pre-reloc;
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};
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&pinctrl {
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u-boot,dm-pre-reloc;
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};
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&scif2 {
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u-boot,dm-pre-reloc;
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clock = <66666666>; /* ToDo: Replace by DM clock driver */
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};
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&scif2_pins {
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u-boot,dm-pre-reloc;
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};
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@ -0,0 +1,134 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the GR-Peach board
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*
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* Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
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* Copyright (C) 2016 Renesas Electronics
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*/
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/dts-v1/;
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#include "r7s72100.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
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/ {
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model = "GR-Peach";
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compatible = "renesas,gr-peach", "renesas,r7s72100";
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aliases {
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serial0 = &scif2;
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};
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chosen {
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bootargs = "ignore_loglevel rw root=/dev/mtdblock0";
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stdout-path = "serial0:115200n8";
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};
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memory@20000000 {
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device_type = "memory";
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reg = <0x20000000 0x00a00000>;
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};
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lbsc {
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#address-cells = <1>;
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#size-cells = <1>;
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};
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flash@18000000 {
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compatible = "mtd-rom";
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probe-type = "map_rom";
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reg = <0x18000000 0x00800000>;
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bank-width = <4>;
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device-width = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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rootfs@600000 {
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label = "rootfs";
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reg = <0x00600000 0x00200000>;
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};
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};
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leds {
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status = "okay";
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compatible = "gpio-leds";
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led1 {
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gpios = <&port6 12 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&pinctrl {
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scif2_pins: serial2 {
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/* P6_2 as RxD2; P6_3 as TxD2 */
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pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
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};
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ether_pins: ether {
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/* Ethernet on Ports 1,3,5,10 */
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pinmux = <RZA1_PINMUX(1, 14, 4)>, /* P1_14 = ET_COL */
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<RZA1_PINMUX(3, 0, 2)>, /* P3_0 = ET_TXCLK */
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<RZA1_PINMUX(3, 3, 2)>, /* P3_3 = ET_MDIO */
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<RZA1_PINMUX(3, 4, 2)>, /* P3_4 = ET_RXCLK */
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<RZA1_PINMUX(3, 5, 2)>, /* P3_5 = ET_RXER */
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<RZA1_PINMUX(3, 6, 2)>, /* P3_6 = ET_RXDV */
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<RZA1_PINMUX(5, 9, 2)>, /* P5_9 = ET_MDC */
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<RZA1_PINMUX(10, 1, 4)>, /* P10_1 = ET_TXER */
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<RZA1_PINMUX(10, 2, 4)>, /* P10_2 = ET_TXEN */
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<RZA1_PINMUX(10, 3, 4)>, /* P10_3 = ET_CRS */
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<RZA1_PINMUX(10, 4, 4)>, /* P10_4 = ET_TXD0 */
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<RZA1_PINMUX(10, 5, 4)>, /* P10_5 = ET_TXD1 */
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<RZA1_PINMUX(10, 6, 4)>, /* P10_6 = ET_TXD2 */
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<RZA1_PINMUX(10, 7, 4)>, /* P10_7 = ET_TXD3 */
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<RZA1_PINMUX(10, 8, 4)>, /* P10_8 = ET_RXD0 */
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<RZA1_PINMUX(10, 9, 4)>, /* P10_9 = ET_RXD1 */
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<RZA1_PINMUX(10, 10, 4)>,/* P10_10 = ET_RXD2 */
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<RZA1_PINMUX(10, 11, 4)>;/* P10_11 = ET_RXD3 */
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};
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};
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&extal_clk {
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clock-frequency = <13333000>;
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};
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&usb_x1_clk {
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clock-frequency = <48000000>;
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};
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&mtu2 {
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status = "okay";
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};
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&ostm0 {
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status = "okay";
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};
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&ostm1 {
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status = "okay";
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};
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&scif2 {
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pinctrl-names = "default";
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pinctrl-0 = <&scif2_pins>;
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status = "okay";
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};
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ðer {
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pinctrl-names = "default";
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pinctrl-0 = <ðer_pins>;
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status = "okay";
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renesas,no-ether-link;
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phy-handle = <&phy0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>;
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reset-delay-us = <5>;
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};
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};
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@ -13,9 +13,16 @@ config CPU_RZA1
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choice
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prompt "Renesas RZ/A1 board select"
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# Renesas Supported Boards
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config TARGET_GRPEACH
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bool "GR-PEACH board"
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endchoice
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config SYS_SOC
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default "rmobile"
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# Renesas Supported Boards
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source "board/renesas/grpeach/Kconfig"
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endif
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@ -0,0 +1,12 @@
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if TARGET_GRPEACH
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config SYS_BOARD
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default "grpeach"
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config SYS_VENDOR
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default "renesas"
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config SYS_CONFIG_NAME
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default "grpeach"
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endif
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@ -0,0 +1,6 @@
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GRPEACH BOARD
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M: Marek Vasut <marek.vasut@gmail.com>
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S: Maintained
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F: board/renesas/grpeach/
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F: include/configs/grpeach.h
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F: configs/grpeach_defconfig
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@ -0,0 +1,8 @@
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#
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# Copyright (C) 2017 Renesas Electronics
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# Copyright (C) 2017 Chris Brandt
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#
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# SPDX-License-Identifier: GPL-2.0+
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obj-y := grpeach.o
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obj-y += lowlevel_init.o
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@ -0,0 +1,52 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Renesas Electronics
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* Copyright (C) Chris Brandt
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#define RZA1_WDT_BASE 0xfcfe0000
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#define WTCSR 0x00
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#define WTCNT 0x02
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#define WRCSR 0x04
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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/* Dummy read (must read WRCSR:WOVF at least once before clearing) */
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readb(RZA1_WDT_BASE + WRCSR);
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writew(0xa500, RZA1_WDT_BASE + WRCSR);
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writew(0x5a5f, RZA1_WDT_BASE + WRCSR);
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writew(0x5a00, RZA1_WDT_BASE + WTCNT);
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writew(0xa578, RZA1_WDT_BASE + WTCSR);
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for (;;)
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asm volatile("wfi");
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}
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@ -0,0 +1,107 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2017 Renesas Electronics
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* Copyright (C) 2017 Chris Brandt
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/macro.h>
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/* Watchdog Registers */
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#define RZA1_WDT_BASE 0xFCFE0000
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#define WTCSR (RZA1_WDT_BASE + 0x00) /* Watchdog Timer Control Register */
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#define WTCNT (RZA1_WDT_BASE + 0x02) /* Watchdog Timer Counter Register */
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#define WRCSR (RZA1_WDT_BASE + 0x04) /* Watchdog Reset Control Register */
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/* Standby controller registers (chapter 55) */
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#define RZA1_STBCR_BASE 0xFCFE0020
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#define STBCR1 (RZA1_STBCR_BASE + 0x00)
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#define STBCR2 (RZA1_STBCR_BASE + 0x04)
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#define STBCR3 (RZA1_STBCR_BASE + 0x400)
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#define STBCR4 (RZA1_STBCR_BASE + 0x404)
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#define STBCR5 (RZA1_STBCR_BASE + 0x408)
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#define STBCR6 (RZA1_STBCR_BASE + 0x40c)
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#define STBCR7 (RZA1_STBCR_BASE + 0x410)
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#define STBCR8 (RZA1_STBCR_BASE + 0x414)
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#define STBCR9 (RZA1_STBCR_BASE + 0x418)
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#define STBCR10 (RZA1_STBCR_BASE + 0x41c)
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#define STBCR11 (RZA1_STBCR_BASE + 0x420)
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#define STBCR12 (RZA1_STBCR_BASE + 0x424)
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#define STBCR13 (RZA1_STBCR_BASE + 0x450)
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/* Clock Registers */
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#define RZA1_FRQCR_BASE 0xFCFE0010
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#define FRQCR (RZA1_FRQCR_BASE + 0x00)
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#define FRQCR2 (RZA1_FRQCR_BASE + 0x04)
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#define SYSCR1 0xFCFE0400 /* System control register 1 */
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#define SYSCR2 0xFCFE0404 /* System control register 2 */
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#define SYSCR3 0xFCFE0408 /* System control register 3 */
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/* Disable WDT */
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#define WTCSR_D 0xA518
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#define WTCNT_D 0x5A00
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/* Enable all peripheral clocks */
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#define STBCR3_D 0x00000000
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#define STBCR4_D 0x00000000
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#define STBCR5_D 0x00000000
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#define STBCR6_D 0x00000000
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#define STBCR7_D 0x00000024
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#define STBCR8_D 0x00000005
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#define STBCR9_D 0x00000000
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#define STBCR10_D 0x00000000
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#define STBCR11_D 0x000000c0
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#define STBCR12_D 0x000000f0
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/*
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* Set all system clocks to full speed.
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* On reset, the CPU will be running at 1/2 speed.
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* In the Hardware Manual, see Table 6.3 Settable Frequency Ranges
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*/
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#define FRQCR_D 0x0035
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#define FRQCR2_D 0x0001
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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/* PL310 init */
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write32 0x3fffff80, 0x00000001
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/* Disable WDT */
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write16 WTCSR, WTCSR_D
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write16 WTCNT, WTCNT_D
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/* Set clocks */
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write16 FRQCR, FRQCR_D
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write16 FRQCR2, FRQCR2_D
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/* Enable all peripherals(Standby Control) */
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write8 STBCR3, STBCR3_D
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write8 STBCR4, STBCR4_D
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write8 STBCR5, STBCR5_D
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write8 STBCR6, STBCR6_D
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write8 STBCR7, STBCR7_D
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write8 STBCR8, STBCR8_D
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write8 STBCR9, STBCR9_D
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write8 STBCR10, STBCR10_D
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write8 STBCR11, STBCR11_D
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write8 STBCR12, STBCR12_D
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/* For serial booting, enable read ahead caching to speed things up */
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#define DRCR_0 0x3FEFA00C
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write32 DRCR_0, 0x00010100 /* Read Burst ON, Length=2 */
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/* Enable all internal RAM */
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write8 SYSCR1, 0xFF
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write8 SYSCR2, 0xFF
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write8 SYSCR3, 0xFF
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nop
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/* back to arch calling code */
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mov pc, lr
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.align 4
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@ -0,0 +1,53 @@
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CONFIG_ARM=y
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# CONFIG_SPL_SYS_THUMB_BUILD is not set
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CONFIG_ARCH_RMOBILE=y
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CONFIG_SYS_TEXT_BASE=0x18000000
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CONFIG_RZA1=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_BOOTDELAY=3
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_HUSH_PARSER=y
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# CONFIG_CMD_ELF is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_SNTP=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_MAC_PARTITION=y
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CONFIG_OF_CONTROL=y
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CONFIG_DEFAULT_DEVICE_TREE="r7s72100-gr-peach-u-boot"
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_USE_ENV_SPI_BUS=y
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CONFIG_ENV_SPI_BUS=0
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CONFIG_USE_ENV_SPI_CS=y
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CONFIG_ENV_SPI_CS=0
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CONFIG_USE_ENV_SPI_MAX_HZ=y
|
||||
CONFIG_ENV_SPI_MAX_HZ=50000000
|
||||
CONFIG_USE_ENV_SPI_MODE=y
|
||||
CONFIG_ENV_SPI_MODE=0x0
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_HAVE_BLOCK_DEVICE=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_RZA1_GPIO=y
|
||||
CONFIG_LED=y
|
||||
CONFIG_LED_GPIO=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_SH_ETHER=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_SCIF_CONSOLE=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_RENESAS_RPC_SPI=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_RENESAS_OSTM_TIMER=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Configuration settings for the Renesas GRPEACH board
|
||||
*
|
||||
* Copyright (C) 2017-2019 Renesas Electronics
|
||||
*/
|
||||
|
||||
#ifndef __GRPEACH_H
|
||||
#define __GRPEACH_H
|
||||
|
||||
/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666
|
||||
|
||||
/* Serial Console */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* Miscellaneous */
|
||||
#define CONFIG_SYS_PBSIZE 256
|
||||
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
|
||||
/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x20000000
|
||||
#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024)
|
||||
#define CONFIG_SYS_LOAD_ADDR \
|
||||
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
|
||||
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_OFFSET 0xc0000
|
||||
|
||||
/* Malloc */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
|
||||
/* Kernel Boot */
|
||||
#define CONFIG_BOOTARGS "ignore_loglevel"
|
||||
|
||||
/* Network interface */
|
||||
#define CONFIG_SH_ETHER_USE_PORT 0
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR 0
|
||||
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
|
||||
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
|
||||
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
|
||||
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
#endif /* __GRPEACH_H */
|
||||
Loading…
Reference in New Issue