mirror of
https://github.com/brain-hackers/u-boot-brain
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ba932bc846
Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
53 lines
909 B
C
53 lines
909 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Renesas Electronics
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* Copyright (C) Chris Brandt
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#define RZA1_WDT_BASE 0xfcfe0000
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#define WTCSR 0x00
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#define WTCNT 0x02
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#define WRCSR 0x04
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DECLARE_GLOBAL_DATA_PTR;
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int board_init(void)
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{
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gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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/* Dummy read (must read WRCSR:WOVF at least once before clearing) */
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readb(RZA1_WDT_BASE + WRCSR);
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writew(0xa500, RZA1_WDT_BASE + WRCSR);
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writew(0x5a5f, RZA1_WDT_BASE + WRCSR);
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writew(0x5a00, RZA1_WDT_BASE + WTCNT);
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writew(0xa578, RZA1_WDT_BASE + WTCSR);
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for (;;)
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asm volatile("wfi");
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}
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