mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 21:26:19 +09:00
e3ff9d51ec
Updated the spi_flash framework to handle all sizes of flashes using bank/extd addr reg facility The current implementation in spi_flash supports 3-byte address mode due to this up to 16Mbytes amount of flash is able to access for those flashes which has an actual size of > 16MB. As most of the flashes introduces a bank/extd address registers for accessing the flashes in 16Mbytes of banks if the flash size is > 16Mbytes, this new scheme will add the bank selection feature for performing write/erase operations on all flashes. Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
||
---|---|---|
.. | ||
nand | ||
onenand | ||
spi | ||
ubi | ||
at45.c | ||
cfi_flash.c | ||
cfi_mtd.c | ||
dataflash.c | ||
ftsmc020.c | ||
jedec_flash.c | ||
Makefile | ||
mtdconcat.c | ||
mtdcore.c | ||
mtdpart.c | ||
mw_eeprom.c | ||
st_smi.c |