mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
d90c7ac7a9
LS1046AFRWY board supports LS1046A family SoCs. This patch add base support for this board. Board support's 4GB ddr memory, i2c, micro-click module,microSD card, serial console,qspi nor flash,ifc nand flash,qsgmii network interface, usb 3.0 and serdes interface to support two x1gen3 pcie interface. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
77 lines
2.7 KiB
Plaintext
77 lines
2.7 KiB
Plaintext
Overview
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--------
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The LS1046A Freeway Board (iFRWY) is a high-performance computing,
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evaluation, and development platform that supports the QorIQ LS1046A
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LayerScape Architecture processor. The FRWY-LS1046A provides SW development
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platform for the Freescale LS1046A processor series, with a complete
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debugging environment. The FRWY-LS1046A is lead-free and RoHS-compliant.
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LS1046A SoC Overview
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--------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
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SoC overview.
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FRWY-LS1046A board Overview
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-----------------------
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- SERDES1 Connections, 4 lanes supporting:
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- Lane0: Unused
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- Lane1: Unused
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- Lane2: QSGMII
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- Lane3: Unused
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- SERDES2 Connections, 4 lanes supporting:
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- Lane0: Unused
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- Lane1: PCIe3 with PCIe x1 slot
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- Lane2: Unused
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- Lane3: PCIe3 with PCIe x1 slot
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- DDR Controller
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- 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
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-IFC/Local Bus
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- One 512 MB NAND flash with ECC support
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- USB 3.0
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- Two Type A port
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- SDHC: connects directly to a full microSD slot
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- QSPI: 64 MB high-speed flash Memory for boot code and storage
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- 4 I2C controllers
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- UART
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- Two 4-pin serial ports at up to 115.2 Kbit/s
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- Two DB9 D-Type connectors supporting one Serial port each
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- ARM JTAG support
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Memory map from core's view
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----------------------------
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Start Address End Address Description Size
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0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
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0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
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0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
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0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
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0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
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0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
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0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB
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0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB
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0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M
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0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M
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0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB
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0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
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0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
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0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
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QSPI flash map:
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Start Address End Address Description Size
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0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI + BL2 1MB
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0x00_4010_0000 - 0x00_404F_FFFF FIP Image
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(Bl31 + BL32(optee.
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bin) + Bl33(uboot)
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+ headers for secure
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boot) 4MB
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0x00_4050_0000 - 0x00_405F_FFFF Boot Firmware Env 1MB
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0x00_4060_0000 - 0x00_408F_FFFF Secure boot headers 3MB
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0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB
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0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB
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0x00_409C_0000 - 0x00_409F_FFFF Reserved 256KB
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0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB
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Booting Options
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---------------
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a) QSPI boot
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b) microSD boot
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