armv8: ls1046afrwy: Add support for LS1046AFRWY platform
LS1046AFRWY board supports LS1046A family SoCs. This patch add base support for this board. Board support's 4GB ddr memory, i2c, micro-click module,microSD card, serial console,qspi nor flash,ifc nand flash,qsgmii network interface, usb 3.0 and serdes interface to support two x1gen3 pcie interface. Signed-off-by: Camelia Groza <camelia.groza@nxp.com> Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> Signed-off-by: Pankit Garg <pankit.garg@nxp.com> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Vabhav Sharma
Prabhakar Kushwaha
parent
196fa2efbe
commit
d90c7ac7a9
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@ -1406,6 +1406,20 @@ config TARGET_LS1046ARDB
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development platform that supports the QorIQ LS1046A
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Layerscape Architecture processor.
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config TARGET_LS1046AFRWY
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bool "Support ls1046afrwy"
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select ARCH_LS1046A
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select ARM64
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select ARMV8_MULTIENTRY
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select BOARD_EARLY_INIT_F
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select BOARD_LATE_INIT
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select DM_SPI_FLASH if DM_SPI
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imply SCSI
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help
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Support for Freescale LS1046AFRWY platform.
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The LS1046A Freeway Board (FRWY) is a high-performance
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development platform that supports the QorIQ LS1046A
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Layerscape Architecture processor.
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config TARGET_H2200
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bool "Support h2200"
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select CPU_PXA
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@ -1697,6 +1711,7 @@ source "board/freescale/ls1021aiot/Kconfig"
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source "board/freescale/ls1046aqds/Kconfig"
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source "board/freescale/ls1043ardb/Kconfig"
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source "board/freescale/ls1046ardb/Kconfig"
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source "board/freescale/ls1046afrwy/Kconfig"
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source "board/freescale/ls1012aqds/Kconfig"
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source "board/freescale/ls1012ardb/Kconfig"
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source "board/freescale/ls1012afrdm/Kconfig"
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@ -107,6 +107,7 @@ config PSCI_RESET
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!TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \
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!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
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!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
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!TARGET_LS1046AFRWY && \
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!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
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!TARGET_LX2160AQDS && \
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!ARCH_UNIPHIER && !TARGET_S32V234EVB
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@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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* Copyright 2019 NXP
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*/
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#include <common.h>
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@ -342,6 +342,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
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fsl-ls1046a-qds-duart.dtb \
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fsl-ls1046a-qds-lpuart.dtb \
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fsl-ls1046a-rdb.dtb \
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fsl-ls1046a-frwy.dtb \
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fsl-ls1012a-qds.dtb \
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fsl-ls1012a-rdb.dtb \
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fsl-ls1012a-2g5rdb.dtb \
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@ -0,0 +1,34 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Device Tree Include file for NXP Layerscape-1046A family SoC.
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*
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* Copyright 2019 NXP
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*
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*/
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/dts-v1/;
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/include/ "fsl-ls1046a.dtsi"
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/ {
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model = "LS1046A FRWY Board";
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aliases {
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spi0 = &qspi;
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};
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};
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&qspi {
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bus-num = <0>;
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status = "okay";
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qflash0: mt25qu512abb8esf@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <50000000>;
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reg = <0>;
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};
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};
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@ -0,0 +1,17 @@
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if TARGET_LS1046AFRWY
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config SYS_BOARD
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default "ls1046afrwy"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "fsl-layerscape"
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config SYS_CONFIG_NAME
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default "ls1046afrwy"
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source "board/freescale/common/Kconfig"
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endif
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@ -0,0 +1,7 @@
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LS1046AFRWY BOARD
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M: Pramod Kumar <pramod.kumar_1@nxp.com>
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S: Maintained
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F: board/freescale/ls1046afrwy/
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F: board/freescale/ls1046afrwy/ls1046afrwy.c
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F: include/configs/ls1046afrwy.h
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F: configs/ls1046afrwy_tfa_defconfig
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@ -0,0 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2019 NXP
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obj-y += ddr.o
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obj-y += ls1046afrwy.o
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obj-$(CONFIG_NET) += eth.o
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@ -0,0 +1,76 @@
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Overview
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--------
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The LS1046A Freeway Board (iFRWY) is a high-performance computing,
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evaluation, and development platform that supports the QorIQ LS1046A
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LayerScape Architecture processor. The FRWY-LS1046A provides SW development
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platform for the Freescale LS1046A processor series, with a complete
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debugging environment. The FRWY-LS1046A is lead-free and RoHS-compliant.
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LS1046A SoC Overview
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--------------------
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Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
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SoC overview.
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FRWY-LS1046A board Overview
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-----------------------
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- SERDES1 Connections, 4 lanes supporting:
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- Lane0: Unused
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- Lane1: Unused
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- Lane2: QSGMII
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- Lane3: Unused
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- SERDES2 Connections, 4 lanes supporting:
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- Lane0: Unused
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- Lane1: PCIe3 with PCIe x1 slot
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- Lane2: Unused
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- Lane3: PCIe3 with PCIe x1 slot
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- DDR Controller
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- 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s
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-IFC/Local Bus
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- One 512 MB NAND flash with ECC support
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- USB 3.0
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- Two Type A port
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- SDHC: connects directly to a full microSD slot
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- QSPI: 64 MB high-speed flash Memory for boot code and storage
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- 4 I2C controllers
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- UART
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- Two 4-pin serial ports at up to 115.2 Kbit/s
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- Two DB9 D-Type connectors supporting one Serial port each
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- ARM JTAG support
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Memory map from core's view
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----------------------------
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Start Address End Address Description Size
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0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM 1MB
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0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR 240MB
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0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 64KB
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0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 64KB
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0x00_2000_0000 - 0x00_20FF_FFFF DCSR 16MB
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0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash 64KB
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0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD 4KB
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0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1 2GB
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0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal 128M
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0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal 128M
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0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2 6GB
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0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
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0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
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0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
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QSPI flash map:
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Start Address End Address Description Size
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0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI + BL2 1MB
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0x00_4010_0000 - 0x00_404F_FFFF FIP Image
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(Bl31 + BL32(optee.
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bin) + Bl33(uboot)
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+ headers for secure
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boot) 4MB
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0x00_4050_0000 - 0x00_405F_FFFF Boot Firmware Env 1MB
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0x00_4060_0000 - 0x00_408F_FFFF Secure boot headers 3MB
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0x00_4090_0000 - 0x00_4093_FFFF FMan ucode 256KB
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0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware 256KB
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0x00_409C_0000 - 0x00_409F_FFFF Reserved 256KB
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0x00_4100_0000 - 0x00_43FF_FFFF FIT Image 48MB
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Booting Options
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---------------
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a) QSPI boot
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b) microSD boot
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@ -0,0 +1,19 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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DECLARE_GLOBAL_DATA_PTR;
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int fsl_initdram(void)
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{
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gd->ram_size = tfa_get_dram_size();
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if (!gd->ram_size)
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gd->ram_size = fsl_ddr_sdram_size();
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return 0;
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}
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@ -0,0 +1,114 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <netdev.h>
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#include <fm_eth.h>
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#include <fsl_dtsec.h>
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#include <fsl_mdio.h>
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#include <malloc.h>
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#include "../common/fman.h"
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_FMAN_ENET
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struct memac_mdio_info dtsec_mdio_info;
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struct mii_dev *dev;
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u32 srds_s1;
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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srds_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
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srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
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dtsec_mdio_info.regs =
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(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
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dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the 1G MDIO bus */
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fm_memac_mdio_init(bis, &dtsec_mdio_info);
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/* QSGMII on lane B, MAC 6/5/10/1 */
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fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR);
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switch (srds_s1) {
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case 0x3040:
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break;
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default:
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printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n",
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srds_s1);
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break;
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}
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dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
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fm_info_set_mdio(FM1_DTSEC6, dev);
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fm_info_set_mdio(FM1_DTSEC5, dev);
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fm_info_set_mdio(FM1_DTSEC10, dev);
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fm_info_set_mdio(FM1_DTSEC1, dev);
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cpu_eth_init(bis);
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#endif
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return pci_eth_init(bis);
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}
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#ifdef CONFIG_FMAN_ENET
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int fdt_update_ethernet_dt(void *blob)
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{
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u32 srds_s1;
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int i, prop;
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int offset, nodeoff;
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const char *path;
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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srds_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
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srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
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/* Cycle through all aliases */
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for (prop = 0; ; prop++) {
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const char *name;
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/* FDT might have been edited, recompute the offset */
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offset = fdt_first_property_offset(blob,
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fdt_path_offset(blob,
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"/aliases")
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);
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/* Select property number 'prop' */
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for (i = 0; i < prop; i++)
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offset = fdt_next_property_offset(blob, offset);
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if (offset < 0)
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break;
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path = fdt_getprop_by_offset(blob, offset, &name, NULL);
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nodeoff = fdt_path_offset(blob, path);
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switch (srds_s1) {
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case 0x3040:
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if (!strcmp(name, "ethernet1"))
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fdt_status_disabled(blob, nodeoff);
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if (!strcmp(name, "ethernet2"))
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fdt_status_disabled(blob, nodeoff);
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if (!strcmp(name, "ethernet3"))
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fdt_status_disabled(blob, nodeoff);
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if (!strcmp(name, "ethernet6"))
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fdt_status_disabled(blob, nodeoff);
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break;
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default:
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printf("%s:Invalid SerDes prtcl 0x%x for LS1046AFRWY\n",
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__func__, srds_s1);
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break;
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}
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}
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return 0;
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}
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#endif
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@ -0,0 +1,223 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 NXP
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*/
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#include <common.h>
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#include <i2c.h>
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#include <fdt_support.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <asm/arch-fsl-layerscape/fsl_icid.h>
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#include <hwconfig.h>
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#include <ahci.h>
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#include <mmc.h>
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#include <scsi.h>
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#include <fm_eth.h>
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#include <fsl_csu.h>
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#include <fsl_esdhc.h>
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#include <fsl_sec.h>
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#include <fsl_dspi.h>
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#define LS1046A_PORSR1_REG 0x1EE0000
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#define BOOT_SRC_SD 0x20000000
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#define BOOT_SRC_MASK 0xFF800000
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#define BOARD_REV_GPIO 13
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#define USB2_SEL_MASK 0x00000100
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#define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \
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(((word) & 0x00ff0000) >> 8) | \
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(((word) & 0x0000ff00) << 8) | \
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(((word) & 0x000000ff) << 24))
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#define SPI_MCR_REG 0x2100000
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DECLARE_GLOBAL_DATA_PTR;
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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static inline void demux_select_usb2(void)
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{
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u32 val;
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struct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR);
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val = in_be32(&pgpio->gpdir);
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val |= USB2_SEL_MASK;
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out_be32(&pgpio->gpdir, val);
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val = in_be32(&pgpio->gpdat);
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val |= USB2_SEL_MASK;
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out_be32(&pgpio->gpdat, val);
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}
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static inline void set_spi_cs_signal_inactive(void)
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{
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/* default: all CS signals inactive state is high */
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uint mcr_val;
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uint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |
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DSPI_MCR_CRXF | DSPI_MCR_CTXF;
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mcr_val = in_be32(SPI_MCR_REG);
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mcr_val |= DSPI_MCR_HALT;
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out_be32(SPI_MCR_REG, mcr_val);
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out_be32(SPI_MCR_REG, mcr_cfg_val);
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mcr_val = in_be32(SPI_MCR_REG);
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mcr_val &= ~DSPI_MCR_HALT;
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out_be32(SPI_MCR_REG, mcr_val);
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}
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int board_early_init_f(void)
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{
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fsl_lsch2_early_init_f();
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return 0;
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}
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|
||||
static inline uint8_t get_board_version(void)
|
||||
{
|
||||
u8 val;
|
||||
struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
|
||||
|
||||
val = (in_le32(&pgpio->gpdat) >> BOARD_REV_GPIO) & 0x03;
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
static const char *freq[2] = {"100.00MHZ", "100.00MHZ"};
|
||||
u32 boot_src;
|
||||
u8 rev;
|
||||
|
||||
rev = get_board_version();
|
||||
switch (rev) {
|
||||
case 0x00:
|
||||
puts("Board: LS1046AFRWY, Rev: A, boot from ");
|
||||
break;
|
||||
case 0x01:
|
||||
puts("Board: LS1046AFRWY, Rev: B, boot from ");
|
||||
break;
|
||||
default:
|
||||
puts("Board: LS1046AFRWY, Rev: Unknown, boot from ");
|
||||
break;
|
||||
}
|
||||
boot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG));
|
||||
|
||||
if ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD)
|
||||
puts("SD\n");
|
||||
else
|
||||
puts("QSPI\n");
|
||||
printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[0], freq[1]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
#ifdef CONFIG_SECURE_BOOT
|
||||
/*
|
||||
* In case of Secure Boot, the IBR configures the SMMU
|
||||
* to allow only Secure transactions.
|
||||
* SMMU must be reset in bypass mode.
|
||||
* Set the ClientPD bit and Clear the USFCFG Bit
|
||||
*/
|
||||
u32 val;
|
||||
val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
|
||||
out_le32(SMMU_SCR0, val);
|
||||
val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
|
||||
out_le32(SMMU_NSCR0, val);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_CAAM
|
||||
sec_init();
|
||||
#endif
|
||||
|
||||
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_setup_core_volt(u32 vdd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void config_board_mux(void)
|
||||
{
|
||||
#ifdef CONFIG_HAS_FSL_XHCI_USB
|
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
|
||||
u32 usb_pwrfault;
|
||||
/*
|
||||
* USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT
|
||||
* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA
|
||||
*/
|
||||
out_be32(&scfg->rcwpmuxcr0, 0x3300);
|
||||
#ifdef CONFIG_HAS_FSL_IIC3
|
||||
/* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */
|
||||
out_be32(&scfg->rcwpmuxcr0, 0x0000);
|
||||
#endif
|
||||
out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
|
||||
usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
|
||||
SCFG_USBPWRFAULT_USB3_SHIFT) |
|
||||
(SCFG_USBPWRFAULT_DEDICATED <<
|
||||
SCFG_USBPWRFAULT_USB2_SHIFT) |
|
||||
(SCFG_USBPWRFAULT_SHARED <<
|
||||
SCFG_USBPWRFAULT_USB1_SHIFT);
|
||||
out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
|
||||
#ifndef CONFIG_HAS_FSL_IIC3
|
||||
/*
|
||||
* LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input
|
||||
* to select I2C3_USB2_SEL_IO
|
||||
* I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to
|
||||
* I2C3 header (default)
|
||||
* I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to
|
||||
* USB2 port
|
||||
* programmed to select USB2 by setting GPIO3_23 output to one
|
||||
*/
|
||||
demux_select_usb2();
|
||||
#endif
|
||||
#endif
|
||||
set_spi_cs_signal_inactive();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MISC_INIT_R
|
||||
int misc_init_r(void)
|
||||
{
|
||||
config_board_mux();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
u64 base[CONFIG_NR_DRAM_BANKS];
|
||||
u64 size[CONFIG_NR_DRAM_BANKS];
|
||||
|
||||
/* fixup DT for the two DDR banks */
|
||||
base[0] = gd->bd->bi_dram[0].start;
|
||||
size[0] = gd->bd->bi_dram[0].size;
|
||||
base[1] = gd->bd->bi_dram[1].start;
|
||||
size[1] = gd->bd->bi_dram[1].size;
|
||||
|
||||
fdt_fixup_memory_banks(blob, base, size, 2);
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
fdt_fixup_fman_ethernet(blob);
|
||||
#endif
|
||||
|
||||
fdt_fixup_icid(blob);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_TARGET_LS1046AFRWY=y
|
||||
CONFIG_SYS_TEXT_BASE=0x82000000
|
||||
CONFIG_QSPI_AHB_INIT=y
|
||||
CONFIG_TFABOOT=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y
|
||||
CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_NAND=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)"
|
||||
CONFIG_OF_CONTROL=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-frwy"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_DM=y
|
||||
CONFIG_SATA_CEVA=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_DM_PCI=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_LAYERSCAPE=y
|
||||
CONFIG_DM_SCSI=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_FSL_QSPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
|
|
@ -1,6 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2016 Freescale Semiconductor
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#ifndef __LS1046A_COMMON_H
|
||||
|
|
@ -202,6 +203,15 @@
|
|||
#include <config_distro_bootcmd.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TARGET_LS1046AFRWY)
|
||||
#define LS1046A_BOOT_SRC_AND_HDR\
|
||||
"boot_scripts=ls1046afrwy_boot.scr\0" \
|
||||
"boot_script_hdr=hdr_ls1046afrwy_bs.out\0"
|
||||
#else
|
||||
#define LS1046A_BOOT_SRC_AND_HDR\
|
||||
"boot_scripts=ls1046ardb_boot.scr\0" \
|
||||
"boot_script_hdr=hdr_ls1046ardb_bs.out\0"
|
||||
#endif
|
||||
#ifndef SPL_NO_MISC
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
|
|
@ -232,8 +242,7 @@
|
|||
"console=ttyS0,115200\0" \
|
||||
CONFIG_MTDPARTS_DEFAULT "\0" \
|
||||
BOOTENV \
|
||||
"boot_scripts=ls1046ardb_boot.scr\0" \
|
||||
"boot_script_hdr=hdr_ls1046ardb_bs.out\0" \
|
||||
LS1046A_BOOT_SRC_AND_HDR \
|
||||
"scan_dev_for_boot_part=" \
|
||||
"part list ${devtype} ${devnum} devplist; " \
|
||||
"env exists devplist || setenv devplist 1; " \
|
||||
|
|
|
|||
|
|
@ -0,0 +1,136 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#ifndef __LS1046AFRWY_H__
|
||||
#define __LS1046AFRWY_H__
|
||||
|
||||
#include "ls1046a_common.h"
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ 100000000
|
||||
#define CONFIG_DDR_CLK_FREQ 100000000
|
||||
|
||||
#define CONFIG_LAYERSCAPE_NS_ACCESS
|
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
|
||||
|
||||
#define CONFIG_SYS_UBOOT_BASE 0x40100000
|
||||
|
||||
/* IFC */
|
||||
#define CONFIG_FSL_IFC
|
||||
/*
|
||||
* NAND Flash Definitions
|
||||
*/
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE 0x7e800000
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
|
||||
#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
|
||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_NAND \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
|
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
|
||||
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
|
||||
| CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
|
||||
| CSOR_NAND_PB(64)) /* 64 Pages Per Block */
|
||||
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
|
||||
FTIM0_NAND_TWP(0x18) | \
|
||||
FTIM0_NAND_TWCHT(0x7) | \
|
||||
FTIM0_NAND_TWH(0xa))
|
||||
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
|
||||
FTIM1_NAND_TWBE(0x39) | \
|
||||
FTIM1_NAND_TRR(0xe) | \
|
||||
FTIM1_NAND_TRP(0x18))
|
||||
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
|
||||
FTIM2_NAND_TREH(0xa) | \
|
||||
FTIM2_NAND_TWHRE(0x1e))
|
||||
#define CONFIG_SYS_NAND_FTIM3 0x0
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_MTD_NAND_VERIFY_WRITE
|
||||
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
|
||||
|
||||
/* IFC Timing Params */
|
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
|
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
|
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
|
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||
#define I2C_RETIMER_ADDR 0x18
|
||||
|
||||
/* I2C bus multiplexer */
|
||||
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
|
||||
#define I2C_MUX_CH_DEFAULT 0x1 /* Channel 0*/
|
||||
#define I2C_MUX_CH_RTC 0x1 /* Channel 0*/
|
||||
|
||||
/* RTC */
|
||||
#define RTC
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/
|
||||
#define CONFIG_SYS_RTC_BUS_NUM 0
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
|
||||
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
|
||||
#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */
|
||||
|
||||
/* FMan */
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_FMAN_ENET
|
||||
|
||||
#define QSGMII_PORT1_PHY_ADDR 0x1c
|
||||
#define QSGMII_PORT2_PHY_ADDR 0x1d
|
||||
#define QSGMII_PORT3_PHY_ADDR 0x1e
|
||||
#define QSGMII_PORT4_PHY_ADDR 0x1f
|
||||
|
||||
#define FDT_SEQ_MACADDR_FROM_ENV
|
||||
|
||||
#define CONFIG_ETHPRIME "FM1@DTSEC3"
|
||||
|
||||
#endif
|
||||
|
||||
/* QSPI device */
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
#define FSL_QSPI_FLASH_SIZE SZ_64M
|
||||
#define FSL_QSPI_FLASH_NUM 1
|
||||
#endif
|
||||
|
||||
#undef CONFIG_BOOTCOMMAND
|
||||
#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \
|
||||
"env exists secureboot && esbc_halt;;"
|
||||
#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \
|
||||
"env exists secureboot && esbc_halt;"
|
||||
|
||||
#include <asm/fsl_secure_boot.h>
|
||||
|
||||
#endif /* __LS1046AFRWY_H__ */
|
||||
|
|
@ -1,6 +1,7 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2009-2012 Freescale Semiconductor, Inc.
|
||||
* Copyright 2019 NXP
|
||||
*/
|
||||
|
||||
#ifndef __FM_ETH_H__
|
||||
|
|
@ -41,8 +42,19 @@ enum fm_eth_type {
|
|||
FM_ETH_10G_E,
|
||||
};
|
||||
|
||||
/* Historically, on FMan v3 platforms, the first MDIO bus has been used for
|
||||
* Clause 22 PHYs and the second MDIO bus for 10G Clause 45 PHYs (thus the
|
||||
* TGEC name).
|
||||
*
|
||||
* On LS1046A-FRWY, the QSGMII PHY is connected to the second MDIO bus,
|
||||
* and no TGEC ports are present on-board.
|
||||
*/
|
||||
#ifdef CONFIG_SYS_FMAN_V3
|
||||
#ifdef CONFIG_TARGET_LS1046AFRWY
|
||||
#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
|
||||
#else
|
||||
#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)
|
||||
#endif
|
||||
#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)
|
||||
#if (CONFIG_SYS_NUM_FMAN == 2)
|
||||
#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)
|
||||
|
|
|
|||
Loading…
Reference in New Issue