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u-boot-brain/board/freescale/b4860qds
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Suresh Gupta 16d88f415a Enable XAUI interface for B4860QDS 
- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
	The PHY addresses of Teranetics PHY on XAUI riser card are assigned
	based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
	AMC2PEX-2S On B4860QDS, AMC2PEX card decide the PHY addresses on slot1
        and slot2
- Configure MDIO for 10Gig Mac

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-24 16:54:12 -05:00
..
b4860qds_crossbar_con.h powerpc/b4860qds: Added Support for B4860QDS 2013-01-30 11:25:11 -06:00
b4860qds_qixis.h powerpc/b4860qds: Added Support for B4860QDS 2013-01-30 11:25:11 -06:00
b4860qds.c ppc: Move lbc_clk and cpu to arch_global_data 2013-02-04 09:04:57 -05:00
b4860qds.h powerpc/b4860qds: Added Support for B4860QDS 2013-01-30 11:25:11 -06:00
ddr.c powerpc/b4860qds: Assign DDR address in board file 2013-05-14 16:13:25 -05:00
eth_b4860qds.c Enable XAUI interface for B4860QDS 2013-05-24 16:54:12 -05:00
law.c board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M 2013-05-24 16:54:12 -05:00
Makefile powerpc/b4860qds: Added Support for B4860QDS 2013-01-30 11:25:11 -06:00
pci.c powerpc/b4860qds: Added Support for B4860QDS 2013-01-30 11:25:11 -06:00
tlb.c board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M 2013-05-24 16:54:12 -05:00