mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
0dc4ab9c43
This patch adds very basic support for the Octeon III SoCs. Only CFI parallel NOR flash and UART is supported for now. Please note that the basic Octeon port does not include the DDR3/4 initialization yet. This will be added in some follow-up patches later. To still use U-Boot on with this port, the L2 cache (4MiB on Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the prompt on such boards. Signed-off-by: Aaron Williams <awilliams@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
31 lines
740 B
C
31 lines
740 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_MACH_OCTEON_IOREMAP_H
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#define __ASM_MACH_OCTEON_IOREMAP_H
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#include <linux/types.h>
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/*
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* Allow physical addresses to be fixed up to help peripherals located
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* outside the low 32-bit range -- generic pass-through version.
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*/
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static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,
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phys_addr_t size)
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{
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return phys_addr;
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}
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static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
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unsigned long flags)
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{
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return (void __iomem *)(XKPHYS | offset);
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}
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static inline int plat_iounmap(const volatile void __iomem *addr)
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{
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return 0;
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}
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#define _page_cachable_default _CACHE_CACHABLE_NONCOHERENT
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#endif /* __ASM_MACH_OCTEON_IOREMAP_H */
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