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![Jagan Teki](/assets/img/avatar_default.png)
Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
75 lines
1.5 KiB
C
75 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Amarula Solutions.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/ccu.h>
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#include <linux/log2.h>
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static const struct ccu_clk_gate *priv_to_gate(struct ccu_priv *priv,
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unsigned long id)
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{
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return &priv->desc->gates[id];
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}
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static int sunxi_set_gate(struct clk *clk, bool on)
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{
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struct ccu_priv *priv = dev_get_priv(clk->dev);
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const struct ccu_clk_gate *gate = priv_to_gate(priv, clk->id);
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u32 reg;
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if (!(gate->flags & CCU_CLK_F_IS_VALID)) {
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printf("%s: (CLK#%ld) unhandled\n", __func__, clk->id);
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return 0;
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}
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debug("%s: (CLK#%ld) off#0x%x, BIT(%d)\n", __func__,
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clk->id, gate->off, ilog2(gate->bit));
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reg = readl(priv->base + gate->off);
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if (on)
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reg |= gate->bit;
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else
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reg &= ~gate->bit;
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writel(reg, priv->base + gate->off);
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return 0;
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}
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static int sunxi_clk_enable(struct clk *clk)
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{
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return sunxi_set_gate(clk, true);
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}
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static int sunxi_clk_disable(struct clk *clk)
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{
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return sunxi_set_gate(clk, false);
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}
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struct clk_ops sunxi_clk_ops = {
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.enable = sunxi_clk_enable,
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.disable = sunxi_clk_disable,
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};
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int sunxi_clk_probe(struct udevice *dev)
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{
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struct ccu_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr_ptr(dev);
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if (!priv->base)
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return -ENOMEM;
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priv->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
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if (!priv->desc)
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return -EINVAL;
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return 0;
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}
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