mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 03:36:16 +09:00
bb3e5aa289
Add the MMC clock gates and reset bits for all the Allwinner SoCs. This allows them to be used by the MMC driver. We don't advertise the mod clock yet, as this is still handled by the MMC driver. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: add V3S, A80 gates/resets] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
85 lines
2.5 KiB
C
85 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Amarula Solutions.
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* Author: Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/arch/ccu.h>
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#include <dt-bindings/clock/sun50i-a64-ccu.h>
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#include <dt-bindings/reset/sun50i-a64-ccu.h>
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static const struct ccu_clk_gate a64_gates[] = {
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[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
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[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
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[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
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[CLK_BUS_OTG] = GATE(0x060, BIT(23)),
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[CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
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[CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
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[CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
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[CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
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[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
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[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
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[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
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[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
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[CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
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[CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
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[CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
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[CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
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[CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
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[CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
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[CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
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};
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static const struct ccu_reset a64_resets[] = {
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[RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
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[RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
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[RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
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[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
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[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
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[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
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[RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
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[RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
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[RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
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[RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
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[RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
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[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
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[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
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[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
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[RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
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[RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
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};
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static const struct ccu_desc a64_ccu_desc = {
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.gates = a64_gates,
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.resets = a64_resets,
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};
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static int a64_clk_bind(struct udevice *dev)
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{
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return sunxi_reset_bind(dev, ARRAY_SIZE(a64_resets));
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}
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static const struct udevice_id a64_ccu_ids[] = {
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{ .compatible = "allwinner,sun50i-a64-ccu",
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.data = (ulong)&a64_ccu_desc },
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{ }
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};
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U_BOOT_DRIVER(clk_sun50i_a64) = {
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.name = "sun50i_a64_ccu",
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.id = UCLASS_CLK,
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.of_match = a64_ccu_ids,
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.priv_auto_alloc_size = sizeof(struct ccu_priv),
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.ops = &sunxi_clk_ops,
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.probe = sunxi_clk_probe,
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.bind = a64_clk_bind,
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};
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