mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 10:46:15 +09:00
992bcf4f27
Different versions of the SDHI core use either bit 17 or bit 20 for the DTRAEND indication, which can differ even between SoC revisions. Make the DTRAEND bit position part of the driver private data, so that the probe function can set this accordingly. Set this to 20 on Socionext SoCs and either 17 or 20 on Renesas SoCs, depending on the SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
543 lines
14 KiB
C
543 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <fdtdec.h>
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#include <mmc.h>
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#include <dm.h>
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#include <linux/compat.h>
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#include <linux/dma-direction.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <power/regulator.h>
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#include <asm/unaligned.h>
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#include "tmio-common.h"
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#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
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CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
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CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
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/* SCC registers */
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#define RENESAS_SDHI_SCC_DTCNTL 0x800
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#define RENESAS_SDHI_SCC_DTCNTL_TAPEN BIT(0)
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#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16
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#define RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff
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#define RENESAS_SDHI_SCC_TAPSET 0x804
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#define RENESAS_SDHI_SCC_DT2FF 0x808
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#define RENESAS_SDHI_SCC_CKSEL 0x80c
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#define RENESAS_SDHI_SCC_CKSEL_DTSEL BIT(0)
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#define RENESAS_SDHI_SCC_RVSCNTL 0x810
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#define RENESAS_SDHI_SCC_RVSCNTL_RVSEN BIT(0)
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#define RENESAS_SDHI_SCC_RVSREQ 0x814
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#define RENESAS_SDHI_SCC_RVSREQ_RVSERR BIT(2)
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#define RENESAS_SDHI_SCC_SMPCMP 0x818
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#define RENESAS_SDHI_SCC_TMPPORT2 0x81c
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#define RENESAS_SDHI_SCC_TMPPORT2_HS400EN BIT(31)
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#define RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4)
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#define RENESAS_SDHI_MAX_TAP 3
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static unsigned int renesas_sdhi_init_tuning(struct tmio_sd_priv *priv)
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{
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u32 reg;
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/* Initialize SCC */
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tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
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reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
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reg &= ~TMIO_SD_CLKCTL_SCLKEN;
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tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
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/* Set sampling clock selection range */
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tmio_sd_writel(priv, (0x8 << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
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RENESAS_SDHI_SCC_DTCNTL_TAPEN,
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RENESAS_SDHI_SCC_DTCNTL);
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reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
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reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
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tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
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reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
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reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
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tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
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tmio_sd_writel(priv, 0x300 /* scc_tappos */,
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RENESAS_SDHI_SCC_DT2FF);
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reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
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reg |= TMIO_SD_CLKCTL_SCLKEN;
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tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
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/* Read TAPNUM */
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return (tmio_sd_readl(priv, RENESAS_SDHI_SCC_DTCNTL) >>
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RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
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RENESAS_SDHI_SCC_DTCNTL_TAPNUM_MASK;
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}
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static void renesas_sdhi_reset_tuning(struct tmio_sd_priv *priv)
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{
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u32 reg;
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/* Reset SCC */
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reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
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reg &= ~TMIO_SD_CLKCTL_SCLKEN;
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tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
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reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
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reg &= ~RENESAS_SDHI_SCC_CKSEL_DTSEL;
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tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
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reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
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reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
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RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
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tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
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reg = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
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reg |= TMIO_SD_CLKCTL_SCLKEN;
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tmio_sd_writel(priv, reg, TMIO_SD_CLKCTL);
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reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
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reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
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tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
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reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
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reg &= ~RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
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tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
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}
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static int renesas_sdhi_hs400(struct udevice *dev)
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{
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struct tmio_sd_priv *priv = dev_get_priv(dev);
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struct mmc *mmc = mmc_get_mmc_dev(dev);
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bool hs400 = (mmc->selected_mode == MMC_HS_400);
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int ret, taps = hs400 ? priv->nrtaps : 8;
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u32 reg;
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if (taps == 4) /* HS400 on 4tap SoC needs different clock */
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ret = clk_set_rate(&priv->clk, 400000000);
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else
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ret = clk_set_rate(&priv->clk, 200000000);
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if (ret < 0)
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return ret;
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tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
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reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_TMPPORT2);
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if (hs400) {
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reg |= RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
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RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL;
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} else {
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reg &= ~(RENESAS_SDHI_SCC_TMPPORT2_HS400EN |
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RENESAS_SDHI_SCC_TMPPORT2_HS400OSEL);
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}
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tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_TMPPORT2);
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tmio_sd_writel(priv, (taps << RENESAS_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) |
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RENESAS_SDHI_SCC_DTCNTL_TAPEN,
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RENESAS_SDHI_SCC_DTCNTL);
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if (taps == 4) {
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tmio_sd_writel(priv, priv->tap_set >> 1,
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RENESAS_SDHI_SCC_TAPSET);
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} else {
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tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
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}
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reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_CKSEL);
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reg |= RENESAS_SDHI_SCC_CKSEL_DTSEL;
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tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_CKSEL);
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reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
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reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
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tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
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return 0;
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}
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static void renesas_sdhi_prepare_tuning(struct tmio_sd_priv *priv,
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unsigned long tap)
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{
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/* Set sampling clock position */
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tmio_sd_writel(priv, tap, RENESAS_SDHI_SCC_TAPSET);
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}
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static unsigned int renesas_sdhi_compare_scc_data(struct tmio_sd_priv *priv)
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{
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/* Get comparison of sampling data */
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return tmio_sd_readl(priv, RENESAS_SDHI_SCC_SMPCMP);
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}
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static int renesas_sdhi_select_tuning(struct tmio_sd_priv *priv,
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unsigned int tap_num, unsigned int taps,
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unsigned int smpcmp)
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{
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unsigned long tap_cnt; /* counter of tuning success */
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unsigned long tap_start;/* start position of tuning success */
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unsigned long tap_end; /* end position of tuning success */
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unsigned long ntap; /* temporary counter of tuning success */
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unsigned long match_cnt;/* counter of matching data */
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unsigned long i;
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bool select = false;
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u32 reg;
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/* Clear SCC_RVSREQ */
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tmio_sd_writel(priv, 0, RENESAS_SDHI_SCC_RVSREQ);
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/* Merge the results */
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for (i = 0; i < tap_num * 2; i++) {
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if (!(taps & BIT(i))) {
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taps &= ~BIT(i % tap_num);
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taps &= ~BIT((i % tap_num) + tap_num);
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}
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if (!(smpcmp & BIT(i))) {
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smpcmp &= ~BIT(i % tap_num);
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smpcmp &= ~BIT((i % tap_num) + tap_num);
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}
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}
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/*
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* Find the longest consecutive run of successful probes. If that
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* is more than RENESAS_SDHI_MAX_TAP probes long then use the
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* center index as the tap.
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*/
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tap_cnt = 0;
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ntap = 0;
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tap_start = 0;
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tap_end = 0;
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for (i = 0; i < tap_num * 2; i++) {
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if (taps & BIT(i))
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ntap++;
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else {
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if (ntap > tap_cnt) {
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tap_start = i - ntap;
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tap_end = i - 1;
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tap_cnt = ntap;
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}
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ntap = 0;
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}
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}
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if (ntap > tap_cnt) {
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tap_start = i - ntap;
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tap_end = i - 1;
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tap_cnt = ntap;
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}
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/*
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* If all of the TAP is OK, the sampling clock position is selected by
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* identifying the change point of data.
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*/
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if (tap_cnt == tap_num * 2) {
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match_cnt = 0;
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ntap = 0;
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tap_start = 0;
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tap_end = 0;
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for (i = 0; i < tap_num * 2; i++) {
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if (smpcmp & BIT(i))
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ntap++;
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else {
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if (ntap > match_cnt) {
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tap_start = i - ntap;
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tap_end = i - 1;
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match_cnt = ntap;
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}
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ntap = 0;
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}
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}
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if (ntap > match_cnt) {
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tap_start = i - ntap;
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tap_end = i - 1;
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match_cnt = ntap;
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}
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if (match_cnt)
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select = true;
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} else if (tap_cnt >= RENESAS_SDHI_MAX_TAP)
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select = true;
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if (select)
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priv->tap_set = ((tap_start + tap_end) / 2) % tap_num;
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else
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return -EIO;
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/* Set SCC */
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tmio_sd_writel(priv, priv->tap_set, RENESAS_SDHI_SCC_TAPSET);
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/* Enable auto re-tuning */
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reg = tmio_sd_readl(priv, RENESAS_SDHI_SCC_RVSCNTL);
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reg |= RENESAS_SDHI_SCC_RVSCNTL_RVSEN;
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tmio_sd_writel(priv, reg, RENESAS_SDHI_SCC_RVSCNTL);
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return 0;
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}
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int renesas_sdhi_execute_tuning(struct udevice *dev, uint opcode)
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{
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struct tmio_sd_priv *priv = dev_get_priv(dev);
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struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
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struct mmc *mmc = upriv->mmc;
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unsigned int tap_num;
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unsigned int taps = 0, smpcmp = 0;
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int i, ret = 0;
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u32 caps;
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/* Only supported on Renesas RCar */
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if (!(priv->caps & TMIO_SD_CAP_RCAR_UHS))
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return -EINVAL;
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/* clock tuning is not needed for upto 52MHz */
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if (!((mmc->selected_mode == MMC_HS_200) ||
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(mmc->selected_mode == MMC_HS_400) ||
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(mmc->selected_mode == UHS_SDR104) ||
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(mmc->selected_mode == UHS_SDR50)))
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return 0;
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tap_num = renesas_sdhi_init_tuning(priv);
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if (!tap_num)
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/* Tuning is not supported */
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goto out;
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if (tap_num * 2 >= sizeof(taps) * 8) {
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dev_err(dev,
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"Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
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goto out;
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}
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/* Issue CMD19 twice for each tap */
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for (i = 0; i < 2 * tap_num; i++) {
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renesas_sdhi_prepare_tuning(priv, i % tap_num);
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/* Force PIO for the tuning */
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caps = priv->caps;
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priv->caps &= ~TMIO_SD_CAP_DMA_INTERNAL;
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ret = mmc_send_tuning(mmc, opcode, NULL);
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priv->caps = caps;
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if (ret == 0)
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taps |= BIT(i);
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ret = renesas_sdhi_compare_scc_data(priv);
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if (ret == 0)
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smpcmp |= BIT(i);
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mdelay(1);
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}
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ret = renesas_sdhi_select_tuning(priv, tap_num, taps, smpcmp);
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out:
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if (ret < 0) {
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dev_warn(dev, "Tuning procedure failed\n");
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renesas_sdhi_reset_tuning(priv);
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}
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return ret;
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}
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#else
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static int renesas_sdhi_hs400(struct udevice *dev)
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{
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return 0;
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}
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#endif
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static int renesas_sdhi_set_ios(struct udevice *dev)
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{
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struct tmio_sd_priv *priv = dev_get_priv(dev);
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u32 tmp;
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int ret;
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/* Stop the clock before changing its rate to avoid a glitch signal */
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tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
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tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
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tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
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ret = renesas_sdhi_hs400(dev);
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if (ret)
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return ret;
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ret = tmio_sd_set_ios(dev);
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mdelay(10);
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#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
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CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
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CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
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struct mmc *mmc = mmc_get_mmc_dev(dev);
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if ((priv->caps & TMIO_SD_CAP_RCAR_UHS) &&
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(mmc->selected_mode != UHS_SDR104) &&
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(mmc->selected_mode != MMC_HS_200) &&
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(mmc->selected_mode != MMC_HS_400)) {
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renesas_sdhi_reset_tuning(priv);
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}
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#endif
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return ret;
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}
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#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
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static int renesas_sdhi_wait_dat0(struct udevice *dev, int state, int timeout)
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{
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int ret = -ETIMEDOUT;
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bool dat0_high;
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bool target_dat0_high = !!state;
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struct tmio_sd_priv *priv = dev_get_priv(dev);
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timeout = DIV_ROUND_UP(timeout, 10); /* check every 10 us. */
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while (timeout--) {
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dat0_high = !!(tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_DAT0);
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if (dat0_high == target_dat0_high) {
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ret = 0;
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break;
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}
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udelay(10);
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}
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return ret;
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}
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#endif
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static const struct dm_mmc_ops renesas_sdhi_ops = {
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.send_cmd = tmio_sd_send_cmd,
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.set_ios = renesas_sdhi_set_ios,
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.get_cd = tmio_sd_get_cd,
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#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
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CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
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CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
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.execute_tuning = renesas_sdhi_execute_tuning,
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#endif
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#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
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.wait_dat0 = renesas_sdhi_wait_dat0,
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#endif
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};
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#define RENESAS_GEN2_QUIRKS TMIO_SD_CAP_RCAR_GEN2
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#define RENESAS_GEN3_QUIRKS \
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TMIO_SD_CAP_64BIT | TMIO_SD_CAP_RCAR_GEN3 | TMIO_SD_CAP_RCAR_UHS
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static const struct udevice_id renesas_sdhi_match[] = {
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{ .compatible = "renesas,sdhi-r8a7790", .data = RENESAS_GEN2_QUIRKS },
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{ .compatible = "renesas,sdhi-r8a7791", .data = RENESAS_GEN2_QUIRKS },
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{ .compatible = "renesas,sdhi-r8a7792", .data = RENESAS_GEN2_QUIRKS },
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{ .compatible = "renesas,sdhi-r8a7793", .data = RENESAS_GEN2_QUIRKS },
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{ .compatible = "renesas,sdhi-r8a7794", .data = RENESAS_GEN2_QUIRKS },
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{ .compatible = "renesas,sdhi-r8a7795", .data = RENESAS_GEN3_QUIRKS },
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{ .compatible = "renesas,sdhi-r8a7796", .data = RENESAS_GEN3_QUIRKS },
|
|
{ .compatible = "renesas,sdhi-r8a77965", .data = RENESAS_GEN3_QUIRKS },
|
|
{ .compatible = "renesas,sdhi-r8a77970", .data = RENESAS_GEN3_QUIRKS },
|
|
{ .compatible = "renesas,sdhi-r8a77990", .data = RENESAS_GEN3_QUIRKS },
|
|
{ .compatible = "renesas,sdhi-r8a77995", .data = RENESAS_GEN3_QUIRKS },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
static ulong renesas_sdhi_clk_get_rate(struct tmio_sd_priv *priv)
|
|
{
|
|
return clk_get_rate(&priv->clk);
|
|
}
|
|
|
|
static void renesas_sdhi_filter_caps(struct udevice *dev)
|
|
{
|
|
struct tmio_sd_plat *plat = dev_get_platdata(dev);
|
|
struct tmio_sd_priv *priv = dev_get_priv(dev);
|
|
|
|
if (!(priv->caps & TMIO_SD_CAP_RCAR_GEN3))
|
|
return;
|
|
|
|
/* HS400 is not supported on H3 ES1.x and M3W ES1.0,ES1.1 */
|
|
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
|
|
(rmobile_get_cpu_rev_integer() <= 1)) ||
|
|
((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
|
|
(rmobile_get_cpu_rev_integer() == 1) &&
|
|
(rmobile_get_cpu_rev_fraction() <= 1)))
|
|
plat->cfg.host_caps &= ~MMC_MODE_HS400;
|
|
|
|
/* H3 ES2.0 uses 4 tuning taps */
|
|
if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
|
|
(rmobile_get_cpu_rev_integer() == 2))
|
|
priv->nrtaps = 4;
|
|
else
|
|
priv->nrtaps = 8;
|
|
|
|
/* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */
|
|
if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) &&
|
|
(rmobile_get_cpu_rev_integer() <= 1)) ||
|
|
((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) &&
|
|
(rmobile_get_cpu_rev_integer() == 1) &&
|
|
(rmobile_get_cpu_rev_fraction() == 0)))
|
|
priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD;
|
|
else
|
|
priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2;
|
|
}
|
|
|
|
static int renesas_sdhi_probe(struct udevice *dev)
|
|
{
|
|
struct tmio_sd_priv *priv = dev_get_priv(dev);
|
|
u32 quirks = dev_get_driver_data(dev);
|
|
struct fdt_resource reg_res;
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
int ret;
|
|
|
|
priv->clk_get_rate = renesas_sdhi_clk_get_rate;
|
|
|
|
if (quirks == RENESAS_GEN2_QUIRKS) {
|
|
ret = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev),
|
|
"reg", 0, ®_res);
|
|
if (ret < 0) {
|
|
dev_err(dev, "\"reg\" resource not found, ret=%i\n",
|
|
ret);
|
|
return ret;
|
|
}
|
|
|
|
if (fdt_resource_size(®_res) == 0x100)
|
|
quirks |= TMIO_SD_CAP_16BIT;
|
|
}
|
|
|
|
ret = clk_get_by_index(dev, 0, &priv->clk);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to get host clock\n");
|
|
return ret;
|
|
}
|
|
|
|
/* set to max rate */
|
|
ret = clk_set_rate(&priv->clk, 200000000);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to set rate for host clock\n");
|
|
clk_free(&priv->clk);
|
|
return ret;
|
|
}
|
|
|
|
ret = clk_enable(&priv->clk);
|
|
if (ret) {
|
|
dev_err(dev, "failed to enable host clock\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = tmio_sd_probe(dev, quirks);
|
|
|
|
renesas_sdhi_filter_caps(dev);
|
|
|
|
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
|
|
CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
|
|
CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
|
|
if (!ret && (priv->caps & TMIO_SD_CAP_RCAR_UHS))
|
|
renesas_sdhi_reset_tuning(priv);
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
U_BOOT_DRIVER(renesas_sdhi) = {
|
|
.name = "renesas-sdhi",
|
|
.id = UCLASS_MMC,
|
|
.of_match = renesas_sdhi_match,
|
|
.bind = tmio_sd_bind,
|
|
.probe = renesas_sdhi_probe,
|
|
.priv_auto_alloc_size = sizeof(struct tmio_sd_priv),
|
|
.platdata_auto_alloc_size = sizeof(struct tmio_sd_plat),
|
|
.ops = &renesas_sdhi_ops,
|
|
};
|