Paul Burton d608254b0a MIPS: Clear hazard between TagLo writes & cache ops ... Writing to the coprocessor 0 TagLo registers introduces an execution hazard in that we need that write to complete before any cache instructions execute. Ensure that hazard is cleared by inserting an ehb instruction between the TagLo writes & cache op loop. Signed-off-by: Paul Burton <paul.burton@imgtec.com>		2016-09-21 15:04:04 +02:00
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ashldi3.c	dm: mips: Import libgcc components from Linux	2012-08-17 20:13:48 +02:00
ashrdi3.c	dm: mips: Import libgcc components from Linux	2012-08-17 20:13:48 +02:00
bootm.c	libfdt: Introduce new ARCH_FIXUP_FDT option	2016-07-31 19:37:08 -06:00
cache_init.S	MIPS: Clear hazard between TagLo writes & cache ops	2016-09-21 15:04:04 +02:00
cache.c	MIPS: L2 cache support	2016-09-21 15:04:04 +02:00
libgcc.h	dm: mips: Import libgcc components from Linux	2012-08-17 20:13:48 +02:00
lshrdi3.c	dm: mips: Import libgcc components from Linux	2012-08-17 20:13:48 +02:00
Makefile	MIPS: Support dynamic I/O port base address	2016-02-01 22:13:25 +01:00