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https://github.com/brain-hackers/u-boot-brain
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e86463f8e3
This converts the PLMT driver from the riscv-specific timer interface to be a DM-based UCLASS_TIMER driver. The clock-frequency/clocks properties are preferred over timebase-frequency for two reasons. First, properties which affect a device should be located near its binding in the device tree. Using timebase-frequency only really makes sense when the cpu itself is the timer device. This is the case when we read the time from a CSR, but not when there is a separate device. Second, it lets the device use the clock subsystem which adds flexibility. If the device is configured for a different clock speed, the timer can adjust itself. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com>
53 lines
1.1 KiB
C
53 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019, Rick Chen <rick@andestech.com>
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* Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
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*
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* U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
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* The PLMT block holds memory-mapped mtime register
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* associated with timer tick.
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*/
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#include <common.h>
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#include <dm.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <linux/err.h>
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/* mtime register */
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#define MTIME_REG(base) ((ulong)(base))
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static int andes_plmt_get_count(struct udevice *dev, u64 *count)
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{
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*count = readq((void __iomem *)MTIME_REG(dev->priv));
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return 0;
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}
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static const struct timer_ops andes_plmt_ops = {
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.get_count = andes_plmt_get_count,
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};
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static int andes_plmt_probe(struct udevice *dev)
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{
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dev->priv = dev_read_addr_ptr(dev);
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if (!dev->priv)
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return -EINVAL;
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return timer_timebase_fallback(dev);
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}
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static const struct udevice_id andes_plmt_ids[] = {
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{ .compatible = "riscv,plmt0" },
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{ }
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};
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U_BOOT_DRIVER(andes_plmt) = {
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.name = "andes_plmt",
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.id = UCLASS_TIMER,
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.of_match = andes_plmt_ids,
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.ops = &andes_plmt_ops,
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.probe = andes_plmt_probe,
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.flags = DM_FLAG_PRE_RELOC,
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};
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