Sean Anderson d4990a4648 riscv: Match memory barriers between send_ipi_many and handle_ipi ... Without a matching barrier on the write side, the barrier in handle_ipi does nothing. It was entirely possible for the boot hart to write to addr, arg0, and arg1 *after* sending the IPI, because there was no barrier on the sending side. Fixes: 90ae281437 ("riscv: add option to wait for ack from secondary harts in smp functions") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Leo Liang <ycliang@andestech.com>		2020-09-30 08:54:52 +08:00
..
cpu	Revert "riscv: Clear pending interrupts before enabling IPIs"	2020-09-30 08:54:52 +08:00
dts	riscv: Update SiFive device tree for new CLINT driver	2020-09-30 08:54:46 +08:00
include/asm	riscv: Rework Andes PLMT as a UCLASS_TIMER driver	2020-09-30 08:54:45 +08:00
lib	riscv: Match memory barriers between send_ipi_many and handle_ipi	2020-09-30 08:54:52 +08:00
config.mk	kconfig / kbuild: Re-sync with Linux 4.19	2020-04-10 11:18:32 -04:00
Kconfig	riscv: Rework Sifive CLINT as UCLASS_TIMER driver	2020-09-30 08:54:46 +08:00
Makefile	riscv: add Kconfig entries for the code model	2018-12-18 09:56:26 +08:00