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riscv: Rework Sifive CLINT as UCLASS_TIMER driver
This converts the clint driver from the riscv-specific interface to be a DM-based UCLASS_TIMER driver. In addition, the SiFive DDR driver previously implicitly depended on the CLINT to select REGMAP. Unlike Andes's PLMT/PLIC (which AFAIK never have anything pass it a dtb), the SiFive CLINT is part of the device tree passed in by qemu. This device tree doesn't have a clocks or clock-frequency property on clint, so we need to fall back on the timebase-frequency property. Perhaps in the future we can get a clock-frequency property added to the qemu dtb. Unlike with the Andes PLMT, the Sifive CLINT is also an IPI controller. RISCV_SYSCON_CLINT is retained for this purpose. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>
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@ -155,10 +155,6 @@ config 64BIT
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config SIFIVE_CLINT
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bool
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depends on RISCV_MMODE || SPL_RISCV_MMODE
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select REGMAP
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select SYSCON
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select SPL_REGMAP if SPL
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select SPL_SYSCON if SPL
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help
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The SiFive CLINT block holds memory-mapped control and status registers
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associated with software and timer interrupts.
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@ -8,9 +8,9 @@
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <asm/syscon.h>
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#include <linux/err.h>
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@ -24,35 +24,19 @@
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DECLARE_GLOBAL_DATA_PTR;
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int riscv_get_time(u64 *time)
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{
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/* ensure timer register base has a sane value */
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riscv_init_ipi();
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*time = readq((void __iomem *)MTIME_REG(gd->arch.clint));
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return 0;
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}
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int riscv_set_timecmp(int hart, u64 cmp)
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{
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/* ensure timer register base has a sane value */
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riscv_init_ipi();
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writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart));
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return 0;
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}
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int riscv_init_ipi(void)
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{
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if (!gd->arch.clint) {
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long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT);
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int ret;
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struct udevice *dev;
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if (IS_ERR(ret))
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return PTR_ERR(ret);
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gd->arch.clint = ret;
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}
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ret = uclass_get_device_by_driver(UCLASS_TIMER,
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DM_GET_DRIVER(sifive_clint), &dev);
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if (ret)
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return ret;
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gd->arch.clint = dev_read_addr_ptr(dev);
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if (!gd->arch.clint)
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return -EINVAL;
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return 0;
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}
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@ -78,14 +62,36 @@ int riscv_get_ipi(int hart, int *pending)
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return 0;
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}
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static int sifive_clint_get_count(struct udevice *dev, u64 *count)
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{
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*count = readq((void __iomem *)MTIME_REG(dev->priv));
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return 0;
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}
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static const struct timer_ops sifive_clint_ops = {
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.get_count = sifive_clint_get_count,
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};
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static int sifive_clint_probe(struct udevice *dev)
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{
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dev->priv = dev_read_addr_ptr(dev);
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if (!dev->priv)
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return -EINVAL;
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return timer_timebase_fallback(dev);
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}
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static const struct udevice_id sifive_clint_ids[] = {
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{ .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
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{ .compatible = "riscv,clint0" },
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{ }
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};
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U_BOOT_DRIVER(sifive_clint) = {
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.name = "sifive_clint",
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.id = UCLASS_SYSCON,
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.id = UCLASS_TIMER,
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.of_match = sifive_clint_ids,
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.probe = sifive_clint_probe,
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.ops = &sifive_clint_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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