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https://github.com/brain-hackers/u-boot-brain
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67ee3dd35e
Change the parent UART clock to be PLL2, so that U-boot can also boot a Freescale 2.6.35 kernel for mx53. FSL kernel and U-boot changed the UART parent from PLL3 to PLL2 to avoid conflicts with IPU clocks, so that the video resolution can be changed without affecting the UART clock. On a 2.6.35 kernel the serial console is messed up after IPU driver is loaded and this patch fixes this problem. Tested on a mx53loco board booting a FSL kernel and also a mainline kernel. Reported-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> |
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| .. | ||
| am33xx | ||
| exynos | ||
| highbank | ||
| imx-common | ||
| mx5 | ||
| mx6 | ||
| omap-common | ||
| omap3 | ||
| omap4 | ||
| omap5 | ||
| s5p-common | ||
| s5pc1xx | ||
| tegra2 | ||
| u8500 | ||
| cache_v7.c | ||
| config.mk | ||
| cpu.c | ||
| Makefile | ||
| start.S | ||
| syslib.c | ||
| u-boot.lds | ||