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https://github.com/brain-hackers/u-boot-brain
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ARM: EXYNOS: Add support for Exynos5 based SoCs
Samsung's ARM Cortex-A15 based SoCs are known as Exynos5 series of SoCs. This patch adds the support for Exynos5. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Chander Kashyap
Albert ARIBAUD
parent
5e46f83cc3
commit
37bb6d89de
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@ -92,6 +92,72 @@ static unsigned long exynos4_get_pll_clk(int pllreg)
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return fout;
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}
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/* exynos5: return pll clock frequency */
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static unsigned long exynos5_get_pll_clk(int pllreg)
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{
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struct exynos5_clock *clk =
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(struct exynos5_clock *)samsung_get_base_clock();
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unsigned long r, m, p, s, k = 0, mask, fout;
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unsigned int freq;
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switch (pllreg) {
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case APLL:
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r = readl(&clk->apll_con0);
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break;
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case MPLL:
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r = readl(&clk->mpll_con0);
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break;
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case EPLL:
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r = readl(&clk->epll_con0);
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k = readl(&clk->epll_con1);
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break;
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case VPLL:
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r = readl(&clk->vpll_con0);
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k = readl(&clk->vpll_con1);
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break;
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default:
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printf("Unsupported PLL (%d)\n", pllreg);
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return 0;
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}
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/*
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* APLL_CON: MIDV [25:16]
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* MPLL_CON: MIDV [25:16]
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* EPLL_CON: MIDV [24:16]
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* VPLL_CON: MIDV [24:16]
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*/
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if (pllreg == APLL || pllreg == MPLL)
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mask = 0x3ff;
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else
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mask = 0x1ff;
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m = (r >> 16) & mask;
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/* PDIV [13:8] */
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p = (r >> 8) & 0x3f;
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/* SDIV [2:0] */
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s = r & 0x7;
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freq = CONFIG_SYS_CLK_FREQ;
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if (pllreg == EPLL) {
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k = k & 0xffff;
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/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
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fout = (m + k / 65536) * (freq / (p * (1 << s)));
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} else if (pllreg == VPLL) {
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k = k & 0xfff;
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/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
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fout = (m + k / 1024) * (freq / (p * (1 << s)));
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} else {
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if (s < 1)
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s = 1;
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/* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
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fout = m * (freq / (p * (1 << (s - 1))));
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}
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return fout;
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}
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/* exynos4: return ARM clock frequency */
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static unsigned long exynos4_get_arm_clk(void)
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{
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@ -114,6 +180,28 @@ static unsigned long exynos4_get_arm_clk(void)
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return armclk;
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}
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/* exynos5: return ARM clock frequency */
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static unsigned long exynos5_get_arm_clk(void)
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{
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struct exynos5_clock *clk =
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(struct exynos5_clock *)samsung_get_base_clock();
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unsigned long div;
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unsigned long armclk;
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unsigned int arm_ratio;
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unsigned int arm2_ratio;
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div = readl(&clk->div_cpu0);
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/* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
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arm_ratio = (div >> 0) & 0x7;
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arm2_ratio = (div >> 28) & 0x7;
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armclk = get_pll_clk(APLL) / (arm_ratio + 1);
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armclk /= (arm2_ratio + 1);
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return armclk;
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}
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/* exynos4: return pwm clock frequency */
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static unsigned long exynos4_get_pwm_clk(void)
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{
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@ -157,6 +245,27 @@ static unsigned long exynos4_get_pwm_clk(void)
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return pclk;
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}
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/* exynos5: return pwm clock frequency */
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static unsigned long exynos5_get_pwm_clk(void)
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{
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struct exynos5_clock *clk =
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(struct exynos5_clock *)samsung_get_base_clock();
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unsigned long pclk, sclk;
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unsigned int ratio;
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/*
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* CLK_DIV_PERIC3
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* PWM_RATIO [3:0]
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*/
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ratio = readl(&clk->div_peric3);
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ratio = ratio & 0xf;
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sclk = get_pll_clk(MPLL);
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pclk = sclk / (ratio + 1);
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return pclk;
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}
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/* exynos4: return uart clock frequency */
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static unsigned long exynos4_get_uart_clk(int dev_index)
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{
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@ -204,6 +313,53 @@ static unsigned long exynos4_get_uart_clk(int dev_index)
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return uclk;
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}
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/* exynos5: return uart clock frequency */
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static unsigned long exynos5_get_uart_clk(int dev_index)
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{
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struct exynos5_clock *clk =
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(struct exynos5_clock *)samsung_get_base_clock();
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unsigned long uclk, sclk;
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unsigned int sel;
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unsigned int ratio;
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/*
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* CLK_SRC_PERIC0
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* UART0_SEL [3:0]
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* UART1_SEL [7:4]
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* UART2_SEL [8:11]
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* UART3_SEL [12:15]
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* UART4_SEL [16:19]
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* UART5_SEL [23:20]
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*/
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sel = readl(&clk->src_peric0);
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sel = (sel >> (dev_index << 2)) & 0xf;
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if (sel == 0x6)
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sclk = get_pll_clk(MPLL);
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else if (sel == 0x7)
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sclk = get_pll_clk(EPLL);
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else if (sel == 0x8)
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sclk = get_pll_clk(VPLL);
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else
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return 0;
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/*
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* CLK_DIV_PERIC0
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* UART0_RATIO [3:0]
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* UART1_RATIO [7:4]
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* UART2_RATIO [8:11]
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* UART3_RATIO [12:15]
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* UART4_RATIO [16:19]
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* UART5_RATIO [23:20]
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*/
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ratio = readl(&clk->div_peric0);
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ratio = (ratio >> (dev_index << 2)) & 0xf;
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uclk = sclk / (ratio + 1);
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return uclk;
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}
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/* exynos4: set the mmc clock */
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static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
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{
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@ -231,27 +387,69 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
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writel(val, addr);
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}
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/* exynos5: set the mmc clock */
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static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
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{
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struct exynos5_clock *clk =
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(struct exynos5_clock *)samsung_get_base_clock();
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unsigned int addr;
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unsigned int val;
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/*
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* CLK_DIV_FSYS1
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* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
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* CLK_DIV_FSYS2
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* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
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*/
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if (dev_index < 2) {
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addr = (unsigned int)&clk->div_fsys1;
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} else {
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addr = (unsigned int)&clk->div_fsys2;
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dev_index -= 2;
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}
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val = readl(addr);
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val &= ~(0xff << ((dev_index << 4) + 8));
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val |= (div & 0xff) << ((dev_index << 4) + 8);
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writel(val, addr);
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}
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unsigned long get_pll_clk(int pllreg)
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{
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return exynos4_get_pll_clk(pllreg);
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if (cpu_is_exynos5())
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return exynos5_get_pll_clk(pllreg);
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else
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return exynos4_get_pll_clk(pllreg);
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}
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unsigned long get_arm_clk(void)
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{
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return exynos4_get_arm_clk();
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if (cpu_is_exynos5())
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return exynos5_get_arm_clk();
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else
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return exynos4_get_arm_clk();
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}
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unsigned long get_pwm_clk(void)
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{
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return exynos4_get_pwm_clk();
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if (cpu_is_exynos5())
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return exynos5_get_pwm_clk();
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else
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return exynos4_get_pwm_clk();
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}
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unsigned long get_uart_clk(int dev_index)
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{
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return exynos4_get_uart_clk(dev_index);
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if (cpu_is_exynos5())
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return exynos5_get_uart_clk(dev_index);
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else
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return exynos4_get_uart_clk(dev_index);
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}
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void set_mmc_clk(int dev_index, unsigned int div)
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{
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exynos4_set_mmc_clk(dev_index, div);
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if (cpu_is_exynos5())
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exynos5_set_mmc_clk(dev_index, div);
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else
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exynos4_set_mmc_clk(dev_index, div);
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}
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@ -250,6 +250,332 @@ struct exynos4_clock {
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unsigned int div_iem_l2;
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unsigned int div_iem_l1;
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};
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struct exynos5_clock {
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unsigned int apll_lock;
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unsigned char res1[0xfc];
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unsigned int apll_con0;
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unsigned int apll_con1;
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unsigned char res2[0xf8];
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unsigned int src_cpu;
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unsigned char res3[0x1fc];
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unsigned int mux_stat_cpu;
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unsigned char res4[0xfc];
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unsigned int div_cpu0;
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unsigned int div_cpu1;
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unsigned char res5[0xf8];
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unsigned int div_stat_cpu0;
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unsigned int div_stat_cpu1;
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unsigned char res6[0x1f8];
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unsigned int gate_sclk_cpu;
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unsigned char res7[0x1fc];
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unsigned int clkout_cmu_cpu;
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unsigned int clkout_cmu_cpu_div_stat;
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unsigned char res8[0x5f8];
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unsigned int armclk_stopctrl;
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unsigned int atclk_stopctrl;
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unsigned char res9[0x8];
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unsigned int parityfail_status;
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unsigned int parityfail_clear;
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unsigned char res10[0x8];
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unsigned int pwr_ctrl;
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unsigned int pwr_ctr2;
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unsigned char res11[0xd8];
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unsigned int apll_con0_l8;
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unsigned int apll_con0_l7;
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unsigned int apll_con0_l6;
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unsigned int apll_con0_l5;
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unsigned int apll_con0_l4;
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unsigned int apll_con0_l3;
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unsigned int apll_con0_l2;
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unsigned int apll_con0_l1;
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unsigned int iem_control;
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unsigned char res12[0xdc];
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unsigned int apll_con1_l8;
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unsigned int apll_con1_l7;
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unsigned int apll_con1_l6;
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unsigned int apll_con1_l5;
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unsigned int apll_con1_l4;
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unsigned int apll_con1_l3;
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unsigned int apll_con1_l2;
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unsigned int apll_con1_l1;
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unsigned char res13[0xe0];
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unsigned int div_iem_l8;
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unsigned int div_iem_l7;
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unsigned int div_iem_l6;
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unsigned int div_iem_l5;
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unsigned int div_iem_l4;
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unsigned int div_iem_l3;
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unsigned int div_iem_l2;
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unsigned int div_iem_l1;
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unsigned char res14[0x2ce0];
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unsigned int mpll_lock;
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unsigned char res15[0xfc];
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unsigned int mpll_con0;
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unsigned int mpll_con1;
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unsigned char res16[0xf8];
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unsigned int src_core0;
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unsigned int src_core1;
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unsigned char res17[0xf8];
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unsigned int src_mask_core;
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unsigned char res18[0x100];
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unsigned int mux_stat_core1;
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unsigned char res19[0xf8];
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unsigned int div_core0;
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unsigned int div_core1;
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unsigned char res20[0xf8];
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unsigned int div_stat_core0;
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unsigned int div_stat_core1;
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unsigned char res21[0x2f8];
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unsigned int gate_ip_core;
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unsigned char res22[0xfc];
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unsigned int clkout_cmu_core;
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unsigned int clkout_cmu_core_div_stat;
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unsigned char res23[0x5f8];
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unsigned int dcgidx_map0;
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unsigned int dcgidx_map1;
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unsigned int dcgidx_map2;
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unsigned char res24[0x14];
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unsigned int dcgperf_map0;
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unsigned int dcgperf_map1;
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unsigned char res25[0x18];
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unsigned int dvcidx_map;
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unsigned char res26[0x1c];
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unsigned int freq_cpu;
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unsigned int freq_dpm;
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unsigned char res27[0x18];
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unsigned int dvsemclk_en;
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unsigned int maxperf;
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unsigned char res28[0x3478];
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unsigned int div_acp;
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unsigned char res29[0xfc];
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unsigned int div_stat_acp;
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unsigned char res30[0x1fc];
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unsigned int gate_ip_acp;
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unsigned char res31[0x1fc];
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unsigned int clkout_cmu_acp;
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unsigned int clkout_cmu_acp_div_stat;
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unsigned char res32[0x38f8];
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unsigned int div_isp0;
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unsigned int div_isp1;
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unsigned int div_isp2;
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unsigned char res33[0xf4];
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unsigned int div_stat_isp0;
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unsigned int div_stat_isp1;
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unsigned int div_stat_isp2;
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unsigned char res34[0x3f4];
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unsigned int gate_ip_isp0;
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unsigned int gate_ip_isp1;
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unsigned char res35[0xf8];
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unsigned int gate_sclk_isp;
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unsigned char res36[0xc];
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unsigned int mcuisp_pwr_ctrl;
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unsigned char res37[0xec];
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unsigned int clkout_cmu_isp;
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unsigned int clkout_cmu_isp_div_stat;
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unsigned char res38[0x3618];
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unsigned int cpll_lock;
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unsigned char res39[0xc];
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unsigned int epll_lock;
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unsigned char res40[0xc];
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unsigned int vpll_lock;
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unsigned char res41[0xdc];
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unsigned int cpll_con0;
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unsigned int cpll_con1;
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unsigned char res42[0x8];
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unsigned int epll_con0;
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unsigned int epll_con1;
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unsigned int epll_con2;
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unsigned char res43[0x4];
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unsigned int vpll_con0;
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unsigned int vpll_con1;
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unsigned int vpll_con2;
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unsigned char res44[0xc4];
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unsigned int src_top0;
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unsigned int src_top1;
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unsigned int src_top2;
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unsigned int src_top3;
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unsigned int src_gscl;
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unsigned int src_disp0_0;
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unsigned int src_disp0_1;
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unsigned int src_disp1_0;
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unsigned int src_disp1_1;
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unsigned char res46[0xc];
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unsigned int src_mau;
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unsigned int src_fsys;
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unsigned char res47[0x8];
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unsigned int src_peric0;
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unsigned int src_peric1;
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unsigned char res48[0x18];
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unsigned int sclk_src_isp;
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unsigned char res49[0x9c];
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unsigned int src_mask_top;
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unsigned char res50[0xc];
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unsigned int src_mask_gscl;
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unsigned int src_mask_disp0_0;
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unsigned int src_mask_disp0_1;
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unsigned int src_mask_disp1_0;
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unsigned int src_mask_disp1_1;
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unsigned int src_mask_maudio;
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unsigned char res52[0x8];
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unsigned int src_mask_fsys;
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unsigned char res53[0xc];
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unsigned int src_mask_peric0;
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unsigned int src_mask_peric1;
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unsigned char res54[0x18];
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unsigned int src_mask_isp;
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unsigned char res55[0x9c];
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unsigned int mux_stat_top0;
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unsigned int mux_stat_top1;
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unsigned int mux_stat_top2;
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unsigned int mux_stat_top3;
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unsigned char res56[0xf0];
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unsigned int div_top0;
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unsigned int div_top1;
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unsigned char res57[0x8];
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unsigned int div_gscl;
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unsigned int div_disp0_0;
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unsigned int div_disp0_1;
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unsigned int div_disp1_0;
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unsigned int div_disp1_1;
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unsigned char res59[0x8];
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unsigned int div_gen;
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unsigned char res60[0x4];
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unsigned int div_mau;
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unsigned int div_fsys0;
|
||||
unsigned int div_fsys1;
|
||||
unsigned int div_fsys2;
|
||||
unsigned int div_fsys3;
|
||||
unsigned int div_peric0;
|
||||
unsigned int div_peric1;
|
||||
unsigned int div_peric2;
|
||||
unsigned int div_peric3;
|
||||
unsigned int div_peric4;
|
||||
unsigned int div_peric5;
|
||||
unsigned char res61[0x10];
|
||||
unsigned int sclk_div_isp;
|
||||
unsigned char res62[0xc];
|
||||
unsigned int div2_ratio0;
|
||||
unsigned int div2_ratio1;
|
||||
unsigned char res63[0x8];
|
||||
unsigned int div4_ratio;
|
||||
unsigned char res64[0x6c];
|
||||
unsigned int div_stat_top0;
|
||||
unsigned int div_stat_top1;
|
||||
unsigned char res65[0x8];
|
||||
unsigned int div_stat_gscl;
|
||||
unsigned int div_stat_disp0_0;
|
||||
unsigned int div_stat_disp0_1;
|
||||
unsigned int div_stat_disp1_0;
|
||||
unsigned int div_stat_disp1_1;
|
||||
unsigned char res67[0x8];
|
||||
unsigned int div_stat_gen;
|
||||
unsigned char res68[0x4];
|
||||
unsigned int div_stat_maudio;
|
||||
unsigned int div_stat_fsys0;
|
||||
unsigned int div_stat_fsys1;
|
||||
unsigned int div_stat_fsys2;
|
||||
unsigned int div_stat_fsys3;
|
||||
unsigned int div_stat_peric0;
|
||||
unsigned int div_stat_peric1;
|
||||
unsigned int div_stat_peric2;
|
||||
unsigned int div_stat_peric3;
|
||||
unsigned int div_stat_peric4;
|
||||
unsigned int div_stat_peric5;
|
||||
unsigned char res69[0x10];
|
||||
unsigned int sclk_div_stat_isp;
|
||||
unsigned char res70[0xc];
|
||||
unsigned int div2_stat0;
|
||||
unsigned int div2_stat1;
|
||||
unsigned char res71[0x8];
|
||||
unsigned int div4_stat;
|
||||
unsigned char res72[0x180];
|
||||
unsigned int gate_top_sclk_disp0;
|
||||
unsigned int gate_top_sclk_disp1;
|
||||
unsigned int gate_top_sclk_gen;
|
||||
unsigned char res74[0xc];
|
||||
unsigned int gate_top_sclk_mau;
|
||||
unsigned int gate_top_sclk_fsys;
|
||||
unsigned char res75[0xc];
|
||||
unsigned int gate_top_sclk_peric;
|
||||
unsigned char res76[0x1c];
|
||||
unsigned int gate_top_sclk_isp;
|
||||
unsigned char res77[0xac];
|
||||
unsigned int gate_ip_gscl;
|
||||
unsigned int gate_ip_disp0;
|
||||
unsigned int gate_ip_disp1;
|
||||
unsigned int gate_ip_mfc;
|
||||
unsigned int gate_ip_g3d;
|
||||
unsigned int gate_ip_gen;
|
||||
unsigned char res79[0xc];
|
||||
unsigned int gate_ip_fsys;
|
||||
unsigned char res80[0x4];
|
||||
unsigned int gate_ip_gps;
|
||||
unsigned int gate_ip_peric;
|
||||
unsigned char res81[0xc];
|
||||
unsigned int gate_ip_peris;
|
||||
unsigned char res82[0x1c];
|
||||
unsigned int gate_block;
|
||||
unsigned char res83[0x7c];
|
||||
unsigned int clkout_cmu_top;
|
||||
unsigned int clkout_cmu_top_div_stat;
|
||||
unsigned char res84[0x37f8];
|
||||
unsigned int src_lex;
|
||||
unsigned char res85[0x2fc];
|
||||
unsigned int div_lex;
|
||||
unsigned char res86[0xfc];
|
||||
unsigned int div_stat_lex;
|
||||
unsigned char res87[0x1fc];
|
||||
unsigned int gate_ip_lex;
|
||||
unsigned char res88[0x1fc];
|
||||
unsigned int clkout_cmu_lex;
|
||||
unsigned int clkout_cmu_lex_div_stat;
|
||||
unsigned char res89[0x3af8];
|
||||
unsigned int div_r0x;
|
||||
unsigned char res90[0xfc];
|
||||
unsigned int div_stat_r0x;
|
||||
unsigned char res91[0x1fc];
|
||||
unsigned int gate_ip_r0x;
|
||||
unsigned char res92[0x1fc];
|
||||
unsigned int clkout_cmu_r0x;
|
||||
unsigned int clkout_cmu_r0x_div_stat;
|
||||
unsigned char res94[0x3af8];
|
||||
unsigned int div_r1x;
|
||||
unsigned char res95[0xfc];
|
||||
unsigned int div_stat_r1x;
|
||||
unsigned char res96[0x1fc];
|
||||
unsigned int gate_ip_r1x;
|
||||
unsigned char res97[0x1fc];
|
||||
unsigned int clkout_cmu_r1x;
|
||||
unsigned int clkout_cmu_r1x_div_stat;
|
||||
unsigned char res98[0x3608];
|
||||
unsigned int bpll_lock;
|
||||
unsigned char res99[0xfc];
|
||||
unsigned int bpll_con0;
|
||||
unsigned int bpll_con1;
|
||||
unsigned char res100[0xe8];
|
||||
unsigned int src_cdrex;
|
||||
unsigned char res101[0x1fc];
|
||||
unsigned int mux_stat_cdrex;
|
||||
unsigned char res102[0xfc];
|
||||
unsigned int div_cdrex;
|
||||
unsigned int div_cdrex2;
|
||||
unsigned char res103[0xf8];
|
||||
unsigned int div_stat_cdrex;
|
||||
unsigned char res104[0x2fc];
|
||||
unsigned int gate_ip_cdrex;
|
||||
unsigned char res105[0xc];
|
||||
unsigned int c2c_monitor;
|
||||
unsigned int dmc_pwr_ctrl;
|
||||
unsigned char res106[0x4];
|
||||
unsigned int drex2_pause;
|
||||
unsigned char res107[0xe0];
|
||||
unsigned int clkout_cmu_cdrex;
|
||||
unsigned int clkout_cmu_cdrex_div_stat;
|
||||
unsigned char res108[0x8];
|
||||
unsigned int lpddr3phy_ctrl;
|
||||
unsigned char res109[0xf5f8];
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -22,6 +22,8 @@
|
|||
#ifndef _EXYNOS4_CPU_H
|
||||
#define _EXYNOS4_CPU_H
|
||||
|
||||
#define DEVICE_NOT_AVAILABLE 0
|
||||
|
||||
#define EXYNOS4_ADDR_BASE 0x10000000
|
||||
|
||||
/* EXYNOS4 */
|
||||
|
|
@ -46,7 +48,34 @@
|
|||
#define EXYNOS4_ADC_BASE 0x13910000
|
||||
#define EXYNOS4_PWMTIMER_BASE 0x139D0000
|
||||
#define EXYNOS4_MODEM_BASE 0x13A00000
|
||||
#define EXYNOS4_USBPHY_CONTROL 0x10020704
|
||||
#define EXYNOS4_USBPHY_CONTROL 0x10020704
|
||||
|
||||
#define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
|
||||
|
||||
/* EXYNOS5 */
|
||||
#define EXYNOS5_GPIO_PART4_BASE 0x03860000
|
||||
#define EXYNOS5_PRO_ID 0x10000000
|
||||
#define EXYNOS5_CLOCK_BASE 0x10010000
|
||||
#define EXYNOS5_POWER_BASE 0x10040000
|
||||
#define EXYNOS5_SWRESET 0x10040400
|
||||
#define EXYNOS5_SYSREG_BASE 0x10050000
|
||||
#define EXYNOS5_WATCHDOG_BASE 0x101D0000
|
||||
#define EXYNOS5_DMC_PHY0_BASE 0x10C00000
|
||||
#define EXYNOS5_DMC_PHY1_BASE 0x10C10000
|
||||
#define EXYNOS5_GPIO_PART3_BASE 0x10D10000
|
||||
#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
|
||||
#define EXYNOS5_GPIO_PART1_BASE 0x11400000
|
||||
#define EXYNOS5_MMC_BASE 0x12200000
|
||||
#define EXYNOS5_SROMC_BASE 0x12250000
|
||||
#define EXYNOS5_USBOTG_BASE 0x12480000
|
||||
#define EXYNOS5_USBPHY_BASE 0x12480000
|
||||
#define EXYNOS5_UART_BASE 0x12C00000
|
||||
#define EXYNOS5_PWMTIMER_BASE 0x12DD0000
|
||||
#define EXYNOS5_GPIO_PART2_BASE 0x13400000
|
||||
#define EXYNOS5_FIMD_BASE 0x14400000
|
||||
|
||||
#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
|
||||
#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/io.h>
|
||||
|
|
@ -83,12 +112,15 @@ static inline int cpu_is_##type(void) \
|
|||
}
|
||||
|
||||
IS_SAMSUNG_TYPE(exynos4, 0xc210)
|
||||
IS_SAMSUNG_TYPE(exynos5, 0xc520)
|
||||
|
||||
#define SAMSUNG_BASE(device, base) \
|
||||
static inline unsigned int samsung_get_base_##device(void) \
|
||||
{ \
|
||||
if (cpu_is_exynos4()) \
|
||||
return EXYNOS4_##base; \
|
||||
else if (cpu_is_exynos5()) \
|
||||
return EXYNOS5_##base; \
|
||||
else \
|
||||
return 0; \
|
||||
}
|
||||
|
|
@ -99,6 +131,7 @@ SAMSUNG_BASE(fimd, FIMD_BASE)
|
|||
SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
|
||||
SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
|
||||
SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
|
||||
SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
|
||||
SAMSUNG_BASE(pro_id, PRO_ID)
|
||||
SAMSUNG_BASE(mmc, MMC_BASE)
|
||||
SAMSUNG_BASE(modem, MODEM_BASE)
|
||||
|
|
|
|||
146
arch/arm/include/asm/arch-exynos/dmc.h
Normal file
146
arch/arm/include/asm/arch-exynos/dmc.h
Normal file
|
|
@ -0,0 +1,146 @@
|
|||
#ifndef __DMC_H__
|
||||
#define __DMC_H__
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct exynos5_dmc {
|
||||
unsigned int concontrol;
|
||||
unsigned int memcontrol;
|
||||
unsigned int memconfig0;
|
||||
unsigned int memconfig1;
|
||||
unsigned int directcmd;
|
||||
unsigned int prechconfig;
|
||||
unsigned int phycontrol0;
|
||||
unsigned char res1[0xc];
|
||||
unsigned int pwrdnconfig;
|
||||
unsigned int timingpzq;
|
||||
unsigned int timingref;
|
||||
unsigned int timingrow;
|
||||
unsigned int timingdata;
|
||||
unsigned int timingpower;
|
||||
unsigned int phystatus;
|
||||
unsigned char res2[0x4];
|
||||
unsigned int chipstatus_ch0;
|
||||
unsigned int chipstatus_ch1;
|
||||
unsigned char res3[0x4];
|
||||
unsigned int mrstatus;
|
||||
unsigned char res4[0x8];
|
||||
unsigned int qoscontrol0;
|
||||
unsigned char resr5[0x4];
|
||||
unsigned int qoscontrol1;
|
||||
unsigned char res6[0x4];
|
||||
unsigned int qoscontrol2;
|
||||
unsigned char res7[0x4];
|
||||
unsigned int qoscontrol3;
|
||||
unsigned char res8[0x4];
|
||||
unsigned int qoscontrol4;
|
||||
unsigned char res9[0x4];
|
||||
unsigned int qoscontrol5;
|
||||
unsigned char res10[0x4];
|
||||
unsigned int qoscontrol6;
|
||||
unsigned char res11[0x4];
|
||||
unsigned int qoscontrol7;
|
||||
unsigned char res12[0x4];
|
||||
unsigned int qoscontrol8;
|
||||
unsigned char res13[0x4];
|
||||
unsigned int qoscontrol9;
|
||||
unsigned char res14[0x4];
|
||||
unsigned int qoscontrol10;
|
||||
unsigned char res15[0x4];
|
||||
unsigned int qoscontrol11;
|
||||
unsigned char res16[0x4];
|
||||
unsigned int qoscontrol12;
|
||||
unsigned char res17[0x4];
|
||||
unsigned int qoscontrol13;
|
||||
unsigned char res18[0x4];
|
||||
unsigned int qoscontrol14;
|
||||
unsigned char res19[0x4];
|
||||
unsigned int qoscontrol15;
|
||||
unsigned char res20[0x14];
|
||||
unsigned int ivcontrol;
|
||||
unsigned int wrtra_config;
|
||||
unsigned int rdlvl_config;
|
||||
unsigned char res21[0x8];
|
||||
unsigned int brbrsvconfig;
|
||||
unsigned int brbqosconfig;
|
||||
unsigned int membaseconfig0;
|
||||
unsigned int membaseconfig1;
|
||||
unsigned char res22[0xc];
|
||||
unsigned int wrlvl_config;
|
||||
unsigned char res23[0xc];
|
||||
unsigned int perevcontrol;
|
||||
unsigned int perev0config;
|
||||
unsigned int perev1config;
|
||||
unsigned int perev2config;
|
||||
unsigned int perev3config;
|
||||
unsigned char res24[0xdebc];
|
||||
unsigned int pmnc_ppc_a;
|
||||
unsigned char res25[0xc];
|
||||
unsigned int cntens_ppc_a;
|
||||
unsigned char res26[0xc];
|
||||
unsigned int cntenc_ppc_a;
|
||||
unsigned char res27[0xc];
|
||||
unsigned int intens_ppc_a;
|
||||
unsigned char res28[0xc];
|
||||
unsigned int intenc_ppc_a;
|
||||
unsigned char res29[0xc];
|
||||
unsigned int flag_ppc_a;
|
||||
unsigned char res30[0xac];
|
||||
unsigned int ccnt_ppc_a;
|
||||
unsigned char res31[0xc];
|
||||
unsigned int pmcnt0_ppc_a;
|
||||
unsigned char res32[0xc];
|
||||
unsigned int pmcnt1_ppc_a;
|
||||
unsigned char res33[0xc];
|
||||
unsigned int pmcnt2_ppc_a;
|
||||
unsigned char res34[0xc];
|
||||
unsigned int pmcnt3_ppc_a;
|
||||
};
|
||||
|
||||
struct exynos5_phy_control {
|
||||
unsigned int phy_con0;
|
||||
unsigned int phy_con1;
|
||||
unsigned int phy_con2;
|
||||
unsigned int phy_con3;
|
||||
unsigned int phy_con4;
|
||||
unsigned char res1[4];
|
||||
unsigned int phy_con6;
|
||||
unsigned char res2[4];
|
||||
unsigned int phy_con8;
|
||||
unsigned int phy_con9;
|
||||
unsigned int phy_con10;
|
||||
unsigned char res3[4];
|
||||
unsigned int phy_con12;
|
||||
unsigned int phy_con13;
|
||||
unsigned int phy_con14;
|
||||
unsigned int phy_con15;
|
||||
unsigned int phy_con16;
|
||||
unsigned char res4[4];
|
||||
unsigned int phy_con17;
|
||||
unsigned int phy_con18;
|
||||
unsigned int phy_con19;
|
||||
unsigned int phy_con20;
|
||||
unsigned int phy_con21;
|
||||
unsigned int phy_con22;
|
||||
unsigned int phy_con23;
|
||||
unsigned int phy_con24;
|
||||
unsigned int phy_con25;
|
||||
unsigned int phy_con26;
|
||||
unsigned int phy_con27;
|
||||
unsigned int phy_con28;
|
||||
unsigned int phy_con29;
|
||||
unsigned int phy_con30;
|
||||
unsigned int phy_con31;
|
||||
unsigned int phy_con32;
|
||||
unsigned int phy_con33;
|
||||
unsigned int phy_con34;
|
||||
unsigned int phy_con35;
|
||||
unsigned int phy_con36;
|
||||
unsigned int phy_con37;
|
||||
unsigned int phy_con38;
|
||||
unsigned int phy_con39;
|
||||
unsigned int phy_con40;
|
||||
unsigned int phy_con41;
|
||||
unsigned int phy_con42;
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
|
|
@ -79,6 +79,59 @@ struct exynos4_gpio_part3 {
|
|||
struct s5p_gpio_bank z;
|
||||
};
|
||||
|
||||
struct exynos5_gpio_part1 {
|
||||
struct s5p_gpio_bank a0;
|
||||
struct s5p_gpio_bank a1;
|
||||
struct s5p_gpio_bank a2;
|
||||
struct s5p_gpio_bank b0;
|
||||
struct s5p_gpio_bank b1;
|
||||
struct s5p_gpio_bank b2;
|
||||
struct s5p_gpio_bank b3;
|
||||
struct s5p_gpio_bank c0;
|
||||
struct s5p_gpio_bank c1;
|
||||
struct s5p_gpio_bank c2;
|
||||
struct s5p_gpio_bank c3;
|
||||
struct s5p_gpio_bank d0;
|
||||
struct s5p_gpio_bank d1;
|
||||
struct s5p_gpio_bank y0;
|
||||
struct s5p_gpio_bank y1;
|
||||
struct s5p_gpio_bank y2;
|
||||
struct s5p_gpio_bank y3;
|
||||
struct s5p_gpio_bank y4;
|
||||
struct s5p_gpio_bank y5;
|
||||
struct s5p_gpio_bank y6;
|
||||
struct s5p_gpio_bank res1[0x980];
|
||||
struct s5p_gpio_bank x0;
|
||||
struct s5p_gpio_bank x1;
|
||||
struct s5p_gpio_bank x2;
|
||||
struct s5p_gpio_bank x3;
|
||||
};
|
||||
|
||||
struct exynos5_gpio_part2 {
|
||||
struct s5p_gpio_bank e0;
|
||||
struct s5p_gpio_bank e1;
|
||||
struct s5p_gpio_bank f0;
|
||||
struct s5p_gpio_bank f1;
|
||||
struct s5p_gpio_bank g0;
|
||||
struct s5p_gpio_bank g1;
|
||||
struct s5p_gpio_bank g2;
|
||||
struct s5p_gpio_bank h0;
|
||||
struct s5p_gpio_bank h1;
|
||||
};
|
||||
|
||||
struct exynos5_gpio_part3 {
|
||||
struct s5p_gpio_bank v0;
|
||||
struct s5p_gpio_bank v1;
|
||||
struct s5p_gpio_bank v2;
|
||||
struct s5p_gpio_bank v3;
|
||||
struct s5p_gpio_bank res1[0x20];
|
||||
struct s5p_gpio_bank v4;
|
||||
};
|
||||
|
||||
struct exynos5_gpio_part4 {
|
||||
struct s5p_gpio_bank z;
|
||||
};
|
||||
|
||||
/* functions */
|
||||
void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
|
||||
void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
|
||||
|
|
@ -98,21 +151,55 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
|
|||
- EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
* GPIO_PER_BANK) + pin)
|
||||
|
||||
#define GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
|
||||
#define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
|
||||
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
|
||||
|
||||
#define exynos4_gpio_part2_get_nr(bank, pin) \
|
||||
(((((((unsigned int) &(((struct exynos4_gpio_part2 *) \
|
||||
EXYNOS4_GPIO_PART2_BASE)->bank)) \
|
||||
- EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
* GPIO_PER_BANK) + pin) + GPIO_PART1_MAX)
|
||||
* GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
|
||||
|
||||
#define exynos5_gpio_part1_get_nr(bank, pin) \
|
||||
((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
|
||||
EXYNOS5_GPIO_PART1_BASE)->bank)) \
|
||||
- EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
* GPIO_PER_BANK) + pin)
|
||||
|
||||
#define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \
|
||||
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
|
||||
|
||||
#define exynos5_gpio_part2_get_nr(bank, pin) \
|
||||
(((((((unsigned int) &(((struct exynos5_gpio_part2 *) \
|
||||
EXYNOS5_GPIO_PART2_BASE)->bank)) \
|
||||
- EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
* GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX)
|
||||
|
||||
#define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \
|
||||
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
|
||||
|
||||
#define exynos5_gpio_part3_get_nr(bank, pin) \
|
||||
(((((((unsigned int) &(((struct exynos5_gpio_part3 *) \
|
||||
EXYNOS5_GPIO_PART3_BASE)->bank)) \
|
||||
- EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
|
||||
* GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
|
||||
|
||||
static inline unsigned int s5p_gpio_base(int nr)
|
||||
{
|
||||
if (nr < GPIO_PART1_MAX)
|
||||
return EXYNOS4_GPIO_PART1_BASE;
|
||||
else
|
||||
return EXYNOS4_GPIO_PART2_BASE;
|
||||
if (cpu_is_exynos5()) {
|
||||
if (nr < EXYNOS5_GPIO_PART1_MAX)
|
||||
return EXYNOS5_GPIO_PART1_BASE;
|
||||
else if (nr < EXYNOS5_GPIO_PART2_MAX)
|
||||
return EXYNOS5_GPIO_PART2_BASE;
|
||||
else
|
||||
return EXYNOS5_GPIO_PART3_BASE;
|
||||
|
||||
} else if (cpu_is_exynos4()) {
|
||||
if (nr < EXYNOS4_GPIO_PART1_MAX)
|
||||
return EXYNOS4_GPIO_PART1_BASE;
|
||||
else
|
||||
return EXYNOS4_GPIO_PART2_BASE;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
52
arch/arm/include/asm/arch-exynos/tzpc.h
Normal file
52
arch/arm/include/asm/arch-exynos/tzpc.h
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* (C) Copyright 2012 Samsung Electronics
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __TZPC_H_
|
||||
#define __TZPC_H_
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
struct exynos5_tzpc {
|
||||
unsigned int r0size;
|
||||
char res1[0x7FC];
|
||||
unsigned int decprot0stat;
|
||||
unsigned int decprot0set;
|
||||
unsigned int decprot0clr;
|
||||
unsigned int decprot1stat;
|
||||
unsigned int decprot1set;
|
||||
unsigned int decprot1clr;
|
||||
unsigned int decprot2stat;
|
||||
unsigned int decprot2set;
|
||||
unsigned int decprot2clr;
|
||||
unsigned int decprot3stat;
|
||||
unsigned int decprot3set;
|
||||
unsigned int decprot3clr;
|
||||
char res2[0x7B0];
|
||||
unsigned int periphid0;
|
||||
unsigned int periphid1;
|
||||
unsigned int periphid2;
|
||||
unsigned int periphid3;
|
||||
unsigned int pcellid0;
|
||||
unsigned int pcellid1;
|
||||
unsigned int pcellid2;
|
||||
unsigned int pcellid3;
|
||||
};
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user