Anup Patel d2db2a8fa4 riscv: Add kconfig option to run U-Boot in S-mode ... This patch adds kconfig option RISCV_SMODE to run U-Boot in S-mode. When this opition is enabled we use s<xyz> CSRs instead of m<xyz> CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. In-future, we will have more patches to avoid accessing misa and mhartid CSRs from S-mode. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>		2018-12-05 14:13:53 +08:00
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ax25	riscv: cache: Implement i/dcache [status, enable, disable]	2018-11-26 13:58:01 +08:00
qemu	riscv: cache: Implement i/dcache [status, enable, disable]	2018-11-26 13:58:01 +08:00
cpu.c	riscv: save hart ID and device tree passed by prior boot stage	2018-11-26 13:57:32 +08:00
Makefile	riscv: Make start.S available for all targets	2018-10-03 17:48:14 +08:00
start.S	riscv: Add kconfig option to run U-Boot in S-mode	2018-12-05 14:13:53 +08:00
u-boot.lds	riscv: Make start.S available for all targets	2018-10-03 17:48:14 +08:00