mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 15:26:03 +09:00
d0487da83f
This CPU core is old, no boards using the CPU are left in mainline, it has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
34 lines
750 B
C
34 lines
750 B
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* (C) Copyright 2009
|
|
* Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
|
*
|
|
* (C) Copyright 2007-2012
|
|
* Nobobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
|
*
|
|
* (C) Copyright 2003
|
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/processor.h>
|
|
#include <asm/io.h>
|
|
|
|
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
|
|
#define TSTR 0x4
|
|
#define TCR0 0x10
|
|
#endif /* CONFIG_CPU_SH4 */
|
|
|
|
#define TCR_TPSC 0x07
|
|
#define TSTR_STR0 BIT(0)
|
|
|
|
int timer_init(void)
|
|
{
|
|
writew(readw(TMU_BASE + TCR0) & ~TCR_TPSC, TMU_BASE + TCR0);
|
|
writeb(readb(TMU_BASE + TSTR) & ~TSTR_STR0, TMU_BASE + TSTR);
|
|
writeb(readb(TMU_BASE + TSTR) | TSTR_STR0, TMU_BASE + TSTR);
|
|
|
|
return 0;
|
|
}
|
|
|