sh: sh3: Remove CPU support
This CPU core is old, no boards using the CPU are left in mainline, it has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
89a6b74636
commit
d0487da83f
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@ -1,9 +1,6 @@
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menu "SuperH architecture"
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depends on SH
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config CPU_SH3
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bool
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config CPU_SH4
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bool
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@ -82,7 +79,6 @@ config SYS_ARCH
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default "sh"
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config SYS_CPU
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default "sh3" if CPU_SH3
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default "sh4" if CPU_SH4
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source "arch/sh/lib/Kconfig"
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@ -1,12 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2007
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# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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#
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# (C) Copyright 2007
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# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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obj-y = cpu.o interrupts.o watchdog.o
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@ -1,12 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2000-2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2007
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# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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#
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# (C) Copyright 2007
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# Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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#
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PLATFORM_CPPFLAGS += -m3
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@ -1,67 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007
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* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*
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* (C) Copyright 2007
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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int checkcpu(void)
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{
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puts("CPU: SH3\n");
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return 0;
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}
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int cpu_init(void)
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{
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return 0;
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}
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int cleanup_before_linux(void)
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{
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disable_interrupts();
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return 0;
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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disable_interrupts();
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reset_cpu(0);
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return 0;
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}
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void flush_cache(unsigned long addr, unsigned long size)
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{
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}
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void icache_enable(void)
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{
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}
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void icache_disable(void)
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{
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}
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int icache_status(void)
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{
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return 0;
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}
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void dcache_enable(void)
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{
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}
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void dcache_disable(void)
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{
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}
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int dcache_status(void)
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{
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return 0;
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}
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@ -1,25 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007
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* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*
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* (C) Copyright 2007
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*/
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#include <common.h>
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int interrupt_init(void)
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{
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return 0;
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}
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void enable_interrupts(void)
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{
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}
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int disable_interrupts(void)
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{
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return 0;
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}
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@ -1,26 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2010
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* Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
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*
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* (C) Copyright 2007
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* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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int watchdog_init(void)
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{
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return 0;
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}
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void reset_cpu(unsigned long ignored)
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{
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/* Address error with SR.BL=1 first. */
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trigger_address_error();
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while (1)
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;
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}
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@ -1,30 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2007-2009 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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* (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*/
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#ifndef _ASM_CPU_SH3_H_
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#define _ASM_CPU_SH3_H_
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/* cache control */
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#define CCR_CACHE_STOP 0x00000008
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#define CCR_CACHE_ENABLE 0x00000005
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#define CCR_CACHE_ICI 0x00000008
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#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
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#define CACHE_OC_WAY_SHIFT 13
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#define CACHE_OC_NUM_ENTRIES 256
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#define CACHE_OC_ENTRY_SHIFT 4
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#if defined(CONFIG_CPU_SH7706)
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#include <asm/cpu_sh7706.h>
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#elif defined(CONFIG_CPU_SH7710)
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#include <asm/cpu_sh7710.h>
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#elif defined(CONFIG_CPU_SH7720)
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#include <asm/cpu_sh7720.h>
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#else
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#error "Unknown SH3 variant"
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#endif
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#endif /* _ASM_CPU_SH3_H_ */
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@ -1,50 +0,0 @@
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#ifndef _ASM_CPU_SH7706_H_
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#define _ASM_CPU_SH7706_H_
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#define CACHE_OC_NUM_WAYS 4
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#define CCR_CACHE_INIT 0x0000000D
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/* MMU and Cache control */
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#define MMUCR 0xFFFFFFE0
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#define CCR 0xFFFFFFEC
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/* PFC */
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#define PACR 0xA4050100
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#define PBCR 0xA4050102
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#define PCCR 0xA4050104
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#define PETCR 0xA4050106
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/* Port Data Registers */
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#define PADR 0xA4050120
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#define PBDR 0xA4050122
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#define PCDR 0xA4050124
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/* BSC */
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#define FRQCR 0xffffff80
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#define BCR1 0xffffff60
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#define BCR2 0xffffff62
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#define WCR1 0xffffff64
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#define WCR2 0xffffff66
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#define MCR 0xffffff68
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/* SDRAM controller */
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#define DCR 0xffffff6a
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#define RTCSR 0xffffff6e
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#define RTCNT 0xffffff70
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#define RTCOR 0xffffff72
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#define RFCR 0xffffff74
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#define SDMR 0xFFFFD000
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#define CS3_R 0xFFFFE460
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/* SCIF */
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#define SCSMR_2 0xA4000150
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#define SCIF0_BASE SCSMR_2
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/* Timer */
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#define TMU_BASE 0xFFFFFE90
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/* On chip oscillator circuits */
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#define WTCNT 0xFFFFFF84
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#define WTCSR 0xFFFFFF86
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#endif /* _ASM_CPU_SH7706_H_ */
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@ -1,61 +0,0 @@
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#ifndef _ASM_CPU_SH7710_H_
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#define _ASM_CPU_SH7710_H_
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#define CACHE_OC_NUM_WAYS 4
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#define CCR_CACHE_INIT 0x0000000D
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/* MMU and Cache control */
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#define MMUCR 0xFFFFFFE0
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#define CCR 0xFFFFFFEC
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/* PFC */
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#define PACR 0xA4050100
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#define PBCR 0xA4050102
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#define PCCR 0xA4050104
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#define PETCR 0xA4050106
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/* Port Data Registers */
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#define PADR 0xA4050120
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#define PBDR 0xA4050122
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#define PCDR 0xA4050124
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/* BSC */
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#define CMNCR 0xA4FD0000
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#define CS0BCR 0xA4FD0004
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#define CS2BCR 0xA4FD0008
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#define CS3BCR 0xA4FD000C
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#define CS4BCR 0xA4FD0010
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#define CS5ABCR 0xA4FD0014
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#define CS5BBCR 0xA4FD0018
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#define CS6ABCR 0xA4FD001C
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#define CS6BBCR 0xA4FD0020
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#define CS0WCR 0xA4FD0024
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#define CS2WCR 0xA4FD0028
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#define CS3WCR 0xA4FD002C
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#define CS4WCR 0xA4FD0030
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#define CS5AWCR 0xA4FD0034
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#define CS5BWCR 0xA4FD0038
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#define CS6AWCR 0xA4FD003C
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#define CS6BWCR 0xA4FD0040
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/* SDRAM controller */
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#define SDCR 0xA4FD0044
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#define RTCSR 0xA4FD0048
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#define RTCNT 0xA4FD004C
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#define RTCOR 0xA4FD0050
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/* SCIF */
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#define SCSMR_0 0xA4400000
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#define SCIF0_BASE SCSMR_0
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#define SCSMR_0 0xA4410000
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#define SCIF1_BASE SCSMR_1
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/* Timer */
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#define TMU_BASE 0xA412FE90
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/* On chip oscillator circuits */
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#define FRQCR 0xA415FF80
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#define WTCNT 0xA415FF84
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#define WTCSR 0xA415FF86
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#endif /* _ASM_CPU_SH7710_H_ */
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@ -1,206 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2007 (C)
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* Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*
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* Copyright 2008 (C)
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* Mark Jonas <mark.jonas@de.bosch.com>
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*
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* SH7720 Internal I/O register
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*/
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#ifndef _ASM_CPU_SH7720_H_
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#define _ASM_CPU_SH7720_H_
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#define CACHE_OC_NUM_WAYS 4
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#define CCR_CACHE_INIT 0x0000000B
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/* EXP */
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#define TRA 0xFFFFFFD0
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#define EXPEVT 0xFFFFFFD4
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#define INTEVT 0xFFFFFFD8
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/* MMU */
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#define MMUCR 0xFFFFFFE0
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#define PTEH 0xFFFFFFF0
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#define PTEL 0xFFFFFFF4
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#define TTB 0xFFFFFFF8
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/* CACHE */
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#define CCR 0xFFFFFFEC
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/* INTC */
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#define IPRF 0xA4080000
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#define IPRG 0xA4080002
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#define IPRH 0xA4080004
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#define IPRI 0xA4080006
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#define IPRJ 0xA4080008
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#define IRR5 0xA4080020
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#define IRR6 0xA4080022
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#define IRR7 0xA4080024
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#define IRR8 0xA4080026
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#define IRR9 0xA4080028
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#define IRR0 0xA4140004
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#define IRR1 0xA4140006
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#define IRR2 0xA4140008
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#define IRR3 0xA414000A
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#define IRR4 0xA414000C
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#define ICR1 0xA4140010
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#define ICR2 0xA4140012
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#define PINTER 0xA4140014
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#define IPRC 0xA4140016
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#define IPRD 0xA4140018
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#define IPRE 0xA414001A
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#define ICR0 0xA414FEE0
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#define IPRA 0xA414FEE2
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#define IPRB 0xA414FEE4
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/* BSC */
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#define BSC_BASE 0xA4FD0000
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#define CMNCR (BSC_BASE + 0x00)
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#define CS0BCR (BSC_BASE + 0x04)
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#define CS2BCR (BSC_BASE + 0x08)
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#define CS3BCR (BSC_BASE + 0x0C)
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#define CS4BCR (BSC_BASE + 0x10)
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#define CS5ABCR (BSC_BASE + 0x14)
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#define CS5BBCR (BSC_BASE + 0x18)
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#define CS6ABCR (BSC_BASE + 0x1C)
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#define CS6BBCR (BSC_BASE + 0x20)
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#define CS0WCR (BSC_BASE + 0x24)
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#define CS2WCR (BSC_BASE + 0x28)
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#define CS3WCR (BSC_BASE + 0x2C)
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#define CS4WCR (BSC_BASE + 0x30)
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#define CS5AWCR (BSC_BASE + 0x34)
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#define CS5BWCR (BSC_BASE + 0x38)
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#define CS6AWCR (BSC_BASE + 0x3C)
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#define CS6BWCR (BSC_BASE + 0x40)
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#define SDCR (BSC_BASE + 0x44)
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#define RTCSR (BSC_BASE + 0x48)
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#define RTCNR (BSC_BASE + 0x4C)
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#define RTCOR (BSC_BASE + 0x50)
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#define SDMR2 (BSC_BASE + 0x4000)
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#define SDMR3 (BSC_BASE + 0x5000)
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/* DMAC */
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/* CPG */
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#define UCLKCR 0xA40A0008
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#define FRQCR 0xA415FF80
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/* LOW POWER MODE */
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/* TMU */
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#define TMU_BASE 0xA412FE90
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/* TPU */
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#define TPU_BASE 0xA4480000
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#define TPU_TSTR (TPU_BASE + 0x00)
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#define TPU_TCR0 (TPU_BASE + 0x10)
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#define TPU_TMDR0 (TPU_BASE + 0x14)
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#define TPU_TIOR0 (TPU_BASE + 0x18)
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#define TPU_TIER0 (TPU_BASE + 0x1C)
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#define TPU_TSR0 (TPU_BASE + 0x20)
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#define TPU_TCNT0 (TPU_BASE + 0x24)
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#define TPU_TGRA0 (TPU_BASE + 0x28)
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#define TPU_TGRB0 (TPU_BASE + 0x2C)
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#define TPU_TGRC0 (TPU_BASE + 0x30)
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#define TPU_TGRD0 (TPU_BASE + 0x34)
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#define TPU_TCR1 (TPU_BASE + 0x50)
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#define TPU_TMDR1 (TPU_BASE + 0x54)
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#define TPU_TIOR1 (TPU_BASE + 0x58)
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#define TPU_TIER1 (TPU_BASE + 0x5C)
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#define TPU_TSR1 (TPU_BASE + 0x60)
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#define TPU_TCNT1 (TPU_BASE + 0x64)
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#define TPU_TGRA1 (TPU_BASE + 0x68)
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#define TPU_TGRB1 (TPU_BASE + 0x6C)
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#define TPU_TGRC1 (TPU_BASE + 0x70)
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#define TPU_TGRD1 (TPU_BASE + 0x74)
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#define TPU_TCR2 (TPU_BASE + 0x90)
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#define TPU_TMDR2 (TPU_BASE + 0x94)
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#define TPU_TIOR2 (TPU_BASE + 0x98)
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#define TPU_TIER2 (TPU_BASE + 0x9C)
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#define TPU_TSR2 (TPU_BASE + 0xB0)
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#define TPU_TCNT2 (TPU_BASE + 0xB4)
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#define TPU_TGRA2 (TPU_BASE + 0xB8)
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#define TPU_TGRB2 (TPU_BASE + 0xBC)
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#define TPU_TGRC2 (TPU_BASE + 0xC0)
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#define TPU_TGRD2 (TPU_BASE + 0xC4)
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#define TPU_TCR3 (TPU_BASE + 0xD0)
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#define TPU_TMDR3 (TPU_BASE + 0xD4)
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#define TPU_TIOR3 (TPU_BASE + 0xD8)
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#define TPU_TIER3 (TPU_BASE + 0xDC)
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#define TPU_TSR3 (TPU_BASE + 0xE0)
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#define TPU_TCNT3 (TPU_BASE + 0xE4)
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#define TPU_TGRA3 (TPU_BASE + 0xE8)
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#define TPU_TGRB3 (TPU_BASE + 0xEC)
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#define TPU_TGRC3 (TPU_BASE + 0xF0)
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#define TPU_TGRD3 (TPU_BASE + 0xF4)
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/* CMT */
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/* SIOF */
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/* SCIF */
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#define SCIF0_BASE 0xA4430000
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/* SIM */
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/* IrDA */
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/* IIC */
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/* LCDC */
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/* USBF */
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/* MMCIF */
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/* PFC */
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#define PFC_BASE 0xA4050100
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#define PACR (PFC_BASE + 0x00)
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#define PBCR (PFC_BASE + 0x02)
|
||||
#define PCCR (PFC_BASE + 0x04)
|
||||
#define PDCR (PFC_BASE + 0x06)
|
||||
#define PECR (PFC_BASE + 0x08)
|
||||
#define PFCR (PFC_BASE + 0x0A)
|
||||
#define PGCR (PFC_BASE + 0x0C)
|
||||
#define PHCR (PFC_BASE + 0x0E)
|
||||
#define PJCR (PFC_BASE + 0x10)
|
||||
#define PKCR (PFC_BASE + 0x12)
|
||||
#define PLCR (PFC_BASE + 0x14)
|
||||
#define PMCR (PFC_BASE + 0x16)
|
||||
#define PPCR (PFC_BASE + 0x18)
|
||||
#define PRCR (PFC_BASE + 0x1A)
|
||||
#define PSCR (PFC_BASE + 0x1C)
|
||||
#define PTCR (PFC_BASE + 0x1E)
|
||||
#define PUCR (PFC_BASE + 0x20)
|
||||
#define PVCR (PFC_BASE + 0x22)
|
||||
#define PSELA (PFC_BASE + 0x24)
|
||||
#define PSELB (PFC_BASE + 0x26)
|
||||
#define PSELC (PFC_BASE + 0x28)
|
||||
#define PSELD (PFC_BASE + 0x2A)
|
||||
|
||||
/* I/O Port */
|
||||
#define PORT_BASE 0xA4050100
|
||||
#define PADR (PORT_BASE + 0x40)
|
||||
#define PBDR (PORT_BASE + 0x42)
|
||||
#define PCDR (PORT_BASE + 0x44)
|
||||
#define PDDR (PORT_BASE + 0x46)
|
||||
#define PEDR (PORT_BASE + 0x48)
|
||||
#define PFDR (PORT_BASE + 0x4A)
|
||||
#define PGDR (PORT_BASE + 0x4C)
|
||||
#define PHDR (PORT_BASE + 0x4E)
|
||||
#define PJDR (PORT_BASE + 0x50)
|
||||
#define PKDR (PORT_BASE + 0x52)
|
||||
#define PLDR (PORT_BASE + 0x54)
|
||||
#define PMDR (PORT_BASE + 0x56)
|
||||
#define PPDR (PORT_BASE + 0x58)
|
||||
#define PRDR (PORT_BASE + 0x5A)
|
||||
#define PSDR (PORT_BASE + 0x5C)
|
||||
#define PTDR (PORT_BASE + 0x5E)
|
||||
#define PUDR (PORT_BASE + 0x60)
|
||||
#define PVDR (PORT_BASE + 0x62)
|
||||
|
||||
/* H-UDI */
|
||||
|
||||
#endif /* _ASM_CPU_SH7720_H_ */
|
||||
|
|
@ -1,8 +1,4 @@
|
|||
#ifndef _ASM_SH_PROCESSOR_H_
|
||||
#define _ASM_SH_PROCESSOR_H_
|
||||
#if defined(CONFIG_CPU_SH3)
|
||||
# include <asm/cpu_sh3.h>
|
||||
#elif defined(CONFIG_CPU_SH4)
|
||||
# include <asm/cpu_sh4.h>
|
||||
#endif
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -13,7 +13,6 @@ obj-$(CONFIG_CMD_SH_ZIMAGEBOOT) += zimageboot.o
|
|||
udivsi3-y := udivsi3_i4i-Os.o
|
||||
|
||||
ifneq ($(CONFIG_CC_OPTIMIZE_FOR_SIZE),y)
|
||||
udivsi3-$(CONFIG_CPU_SH3) := udivsi3_i4i.o
|
||||
udivsi3-$(CONFIG_CPU_SH4) := udivsi3_i4i.o
|
||||
endif
|
||||
udivsi3-y += udivsi3.o
|
||||
|
|
|
|||
|
|
@ -14,11 +14,6 @@
|
|||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#if defined(CONFIG_CPU_SH3)
|
||||
#define TSTR 0x2
|
||||
#define TCR0 0xc
|
||||
#endif /* CONFIG_CPU_SH3 */
|
||||
|
||||
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE)
|
||||
#define TSTR 0x4
|
||||
#define TCR0 0x10
|
||||
|
|
|
|||
|
|
@ -23,13 +23,7 @@ U-Boot for Renesas SuperH
|
|||
2.2. Renesas SH7722
|
||||
This CPU has the SH4AL-DSP core.
|
||||
|
||||
2.3. Renesas SH7720
|
||||
This CPU has the SH3 core.
|
||||
|
||||
2.4. Renesas SH7710/SH7712
|
||||
This CPU has the SH3-DSP core and Ethernet controller.
|
||||
|
||||
2.5. Renesas SH7780
|
||||
2.3. Renesas SH7780
|
||||
This CPU has the SH4A core.
|
||||
|
||||
================================================================================
|
||||
|
|
|
|||
|
|
@ -12,28 +12,7 @@ struct uart_port {
|
|||
enum sh_clk_mode clk_mode; /* clock mode */
|
||||
};
|
||||
|
||||
#if defined(CONFIG_CPU_SH7706) || \
|
||||
defined(CONFIG_CPU_SH7707) || \
|
||||
defined(CONFIG_CPU_SH7708) || \
|
||||
defined(CONFIG_CPU_SH7709)
|
||||
# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
|
||||
# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
|
||||
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||
#elif defined(CONFIG_CPU_SH7705)
|
||||
# define SCIF0 0xA4400000
|
||||
# define SCIF2 0xA4410000
|
||||
# define SCSMR_Ir 0xA44A0000
|
||||
# define IRDA_SCIF SCIF0
|
||||
# define SCPCR 0xA4000116
|
||||
# define SCPDR 0xA4000136
|
||||
|
||||
/* Set the clock source,
|
||||
* SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
|
||||
* SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
|
||||
*/
|
||||
# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
|
||||
#elif defined(CONFIG_CPU_SH7720) || \
|
||||
defined(CONFIG_CPU_SH7721) || \
|
||||
#if defined(CONFIG_CPU_SH7721) || \
|
||||
defined(CONFIG_SH73A0) || \
|
||||
defined(CONFIG_R8A7740)
|
||||
# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||
|
|
@ -51,12 +30,6 @@ struct uart_port {
|
|||
# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
|
||||
0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
|
||||
0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
|
||||
#elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
|
||||
# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define PACR 0xa4050100
|
||||
# define PBCR 0xa4050102
|
||||
# define SCSCR_INIT(port) 0x3B
|
||||
#elif defined(CONFIG_CPU_SH7722)
|
||||
# define PADR 0xA4050120
|
||||
# undef PSDR
|
||||
|
|
@ -175,9 +148,7 @@ struct uart_port {
|
|||
#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
|
||||
|
||||
#if defined(CONFIG_CPU_SH7705) || \
|
||||
defined(CONFIG_CPU_SH7720) || \
|
||||
defined(CONFIG_CPU_SH7721) || \
|
||||
#if defined(CONFIG_CPU_SH7721) || \
|
||||
defined(CONFIG_SH73A0) || \
|
||||
defined(CONFIG_R8A7740)
|
||||
# define SCIF_ORER 0x0200
|
||||
|
|
@ -225,9 +196,7 @@ struct uart_port {
|
|||
#define SCxSR_ORER(port)\
|
||||
(((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
|
||||
|
||||
#if defined(CONFIG_CPU_SH7705) || \
|
||||
defined(CONFIG_CPU_SH7720) || \
|
||||
defined(CONFIG_CPU_SH7721) || \
|
||||
#if defined(CONFIG_CPU_SH7721) || \
|
||||
defined(CONFIG_SH73A0) || \
|
||||
defined(CONFIG_R8A7740)
|
||||
# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
|
||||
|
|
@ -309,23 +278,9 @@ static inline void sci_##name##_out(struct uart_port *port,\
|
|||
SCI_OUT(sci_size, sci_offset, value);\
|
||||
}
|
||||
|
||||
#if defined(CONFIG_CPU_SH3) || \
|
||||
defined(CONFIG_SH73A0) || \
|
||||
#if defined(CONFIG_SH73A0) || \
|
||||
defined(CONFIG_R8A7740)
|
||||
#if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
|
||||
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
|
||||
sh4_sci_offset, sh4_sci_size, \
|
||||
sh3_scif_offset, sh3_scif_size, \
|
||||
sh4_scif_offset, sh4_scif_size, \
|
||||
h8_sci_offset, h8_sci_size) \
|
||||
CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
|
||||
sh4_scif_offset, sh4_scif_size)
|
||||
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
|
||||
sh4_scif_offset, sh4_scif_size) \
|
||||
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
|
||||
#elif defined(CONFIG_CPU_SH7705) || \
|
||||
defined(CONFIG_CPU_SH7720) || \
|
||||
defined(CONFIG_CPU_SH7721) || \
|
||||
#if defined(CONFIG_CPU_SH7721) || \
|
||||
defined(CONFIG_SH73A0)
|
||||
#define SCIF_FNS(name, scif_offset, scif_size) \
|
||||
CPU_SCIF_FNS(name, scif_offset, scif_size)
|
||||
|
|
@ -368,9 +323,7 @@ static inline void sci_##name##_out(struct uart_port *port,\
|
|||
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SH7705) || \
|
||||
defined(CONFIG_CPU_SH7720) || \
|
||||
defined(CONFIG_CPU_SH7721) || \
|
||||
#if defined(CONFIG_CPU_SH7721) || \
|
||||
defined(CONFIG_SH73A0)
|
||||
|
||||
SCIF_FNS(SCSMR, 0x00, 16)
|
||||
|
|
@ -471,17 +424,7 @@ SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */
|
|||
#define sci_in(port, reg) sci_##reg##_in(port)
|
||||
#define sci_out(port, reg, value) sci_##reg##_out(port, value)
|
||||
|
||||
#if defined(CONFIG_CPU_SH7706) || \
|
||||
defined(CONFIG_CPU_SH7707) || \
|
||||
defined(CONFIG_CPU_SH7708) || \
|
||||
defined(CONFIG_CPU_SH7709)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xfffffe80)
|
||||
return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SH7750) || \
|
||||
#if defined(CONFIG_CPU_SH7750) || \
|
||||
defined(CONFIG_CPU_SH7751) || \
|
||||
defined(CONFIG_CPU_SH7751R) || \
|
||||
defined(CONFIG_CPU_SH7750R) || \
|
||||
|
|
@ -533,9 +476,7 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
|
||||
#if defined(CONFIG_CPU_SH7780)
|
||||
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
|
||||
#elif defined(CONFIG_CPU_SH7705) || \
|
||||
defined(CONFIG_CPU_SH7720) || \
|
||||
defined(CONFIG_CPU_SH7721) || \
|
||||
#elif defined(CONFIG_CPU_SH7721) || \
|
||||
defined(CONFIG_SH73A0) || \
|
||||
defined(CONFIG_R8A7740)
|
||||
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
|
||||
|
|
|
|||
|
|
@ -270,8 +270,6 @@ CONFIG_CPU_PXA26X
|
|||
CONFIG_CPU_PXA27X
|
||||
CONFIG_CPU_PXA300
|
||||
CONFIG_CPU_R8000
|
||||
CONFIG_CPU_SH7706
|
||||
CONFIG_CPU_SH7720
|
||||
CONFIG_CPU_SH7722
|
||||
CONFIG_CPU_SH7723
|
||||
CONFIG_CPU_SH7734
|
||||
|
|
@ -4416,7 +4414,6 @@ CONFIG_TWR
|
|||
CONFIG_TWR_P1025
|
||||
CONFIG_TX_DESCR_NUM
|
||||
CONFIG_TZSW_RESERVED_DRAM_SIZE
|
||||
CONFIG_T_SH7706LSR
|
||||
CONFIG_UART_BR_PRELIM
|
||||
CONFIG_UART_OR_PRELIM
|
||||
CONFIG_UBIBLOCK
|
||||
|
|
@ -4515,7 +4512,6 @@ CONFIG_USB_GADGET_OMAP
|
|||
CONFIG_USB_GADGET_PXA27X
|
||||
CONFIG_USB_GADGET_PXA2XX
|
||||
CONFIG_USB_GADGET_SA1100
|
||||
CONFIG_USB_GADGET_SUPERH
|
||||
CONFIG_USB_INVENTRA_DMA
|
||||
CONFIG_USB_ISP1301_I2C_ADDR
|
||||
CONFIG_USB_MAX_CONTROLLER_COUNT
|
||||
|
|
|
|||
Loading…
Reference in New Issue