mirror of
https://github.com/brain-hackers/u-boot-brain
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cf6eb6da43
This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
107 lines
3.3 KiB
ArmAsm
107 lines
3.3 KiB
ArmAsm
/*
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <ppc_asm.tmpl>
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#include <config.h>
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#include <asm/mmu.h>
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/**************************************************************************
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* TLB TABLE
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*
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* This table is used by the cpu boot code to setup the initial tlb
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* entries. Rather than make broad assumptions in the cpu source tree,
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* this table lets each board set things up however they like.
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*
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* Pointer to the table is returned in r1
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*
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*************************************************************************/
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.section .bootpg,"ax"
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.globl tlbtab
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tlbtab:
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tlbtab_start
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/* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */
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tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
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/* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */
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tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0,
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AC_RWX | SA_IG )
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/* TLB#2: TLB-entry for EBC */
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tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_RWX | SA_IG)
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/*
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* TLB#3: BOOT_CS (FLASH) must be forth. Before relocation SA_I can be
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* off to use the speed up boot process. It is patched after relocation
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* to enable SA_I
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*/
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tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_1M, CONFIG_SYS_BOOT_BASE_ADDR, 1,
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AC_RWX | SA_G)
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/*
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* TLB entries for SDRAM are not needed on this platform.
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* They are dynamically generated in the SPD DDR(2) detection
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* routine.
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*/
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/* TLB#4: */
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tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1,
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AC_RW | SA_IG )
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/* TLB#5: */
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tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1,
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AC_RW | SA_IG )
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/* TLB#6: */
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tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1,
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AC_RW | SA_IG )
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/* TLB-entry for Internal Registers & OCM */
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/* TLB#7: */
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tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,
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AC_RWX | SA_IG )
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/*TLB-entry PCI registers*/
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/* TLB#8: */
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tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
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/* TLB-entry for peripherals */
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/* TLB#9: */
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tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
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/* CAN */
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/* TLB#10: */
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tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_RWX | SA_IG )
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/* TLB#11: CPLD and IMC-Standard 32 MB */
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tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_RWX | SA_IG )
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/* TLB#12: */
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tlbentry( CONFIG_SYS_CS_2 + 0x1000000, SZ_16M, CONFIG_SYS_CS_2 + 0x1000000, 1,
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AC_RWX | SA_IG )
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/* IMC-Fast 32 MB */
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/* TLB#13: */
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tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_RWX | SA_IG )
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/* TLB#14: */
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tlbentry( CONFIG_SYS_CS_3 + 0x1000000, SZ_16M, CONFIG_SYS_CS_3, 1,
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AC_RWX | SA_IG )
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tlbtab_end
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