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https://github.com/brain-hackers/u-boot-brain
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ppc4xx: TLB init file cleanup
This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
parent
2a72e9ed18
commit
cf6eb6da43
@ -577,11 +577,16 @@ extern int num_tlb_entries;
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#define SA_M 0x00000200 /* Memory coherence */
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#define SA_G 0x00000100 /* Guarded */
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#define SA_E 0x00000080 /* Endian */
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/* Some additional macros for combinations often used */
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#define SA_IG (SA_I | SA_G)
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/* Access control */
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#define AC_X 0x00000024 /* Execute */
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#define AC_W 0x00000012 /* Write */
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#define AC_R 0x00000009 /* Read */
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/* Some additional macros for combinations often used */
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#define AC_RW (AC_R | AC_W)
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#define AC_RWX (AC_R | AC_W | AC_X)
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/* Some handy macros */
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@ -48,29 +48,29 @@ tlbtab:
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* speed up boot process. It is patched after relocation to enable SA_I
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*/
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#ifndef CONFIG_NAND_SPL
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tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
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tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
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#else
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tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
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tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
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tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G)
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tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
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#endif
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/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
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tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
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tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
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/* PCI base & peripherals */
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tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
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tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
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tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I)
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tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I)
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/* PCI */
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tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG)
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/* USB 2.0 Device */
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tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
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tlbtab_end
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@ -81,7 +81,7 @@ tlbtab:
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*/
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#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
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#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
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#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
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#define TLB02 TLB2(AC_RWX | SA_IG)
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.globl reconfig_tlb0
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reconfig_tlb0:
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@ -47,11 +47,11 @@ tlbtab:
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* enable SA_I
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*/
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#ifndef CONFIG_NAND_SPL
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tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
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tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
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#else
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tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
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tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
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tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
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tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G)
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tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
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tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG)
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#endif
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/*
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@ -62,51 +62,51 @@ tlbtab:
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#ifdef CONFIG_SYS_INIT_RAM_DCACHE
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/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
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tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
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tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
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#endif
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tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
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/* PCIe UTL register */
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tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_RW | SA_IG)
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#if !defined(CONFIG_ARCHES)
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/* TLB-entry for NAND */
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tlbentry(CONFIG_SYS_NAND_ADDR, SZ_16M, CONFIG_SYS_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
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tlbentry(CONFIG_SYS_NAND_ADDR, SZ_16M, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG)
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/* TLB-entry for CPLD */
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tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_RW | SA_IG)
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#else
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/* TLB-entry for FPGA */
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tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_FPGA_BASE, SZ_16M, CONFIG_SYS_FPGA_BASE, 4, AC_RW | SA_IG)
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#endif
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/* TLB-entry for OCM */
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tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
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tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4, AC_RWX | SA_I)
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/* TLB-entry for Local Configuration registers => peripherals */
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tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
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tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
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/* AHB: Internal USB Peripherals (USB, SATA) */
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tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
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tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_RWX | SA_IG)
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#if defined(CONFIG_RAPIDIO)
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/* TLB-entries for RapidIO (SRIO) */
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tlbentry(CONFIG_SYS_SRGPL0_REG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_REG_BAR,
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0xD, AC_R|AC_W|SA_G|SA_I)
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0xD, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_SRGPL0_CFG_BAR, SZ_16M, CONFIG_SYS_SRGPL0_CFG_BAR,
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0xD, AC_R|AC_W|SA_G|SA_I)
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0xD, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_SRGPL0_MNT_BAR, SZ_16M, CONFIG_SYS_SRGPL0_MNT_BAR,
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0xD, AC_R|AC_W|SA_G|SA_I)
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0xD, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_I2ODMA_BASE, SZ_1K, 0x00100000,
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0x4, AC_R|AC_W|SA_G|SA_I)
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0x4, AC_RW | SA_IG)
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#endif
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tlbtab_end
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@ -118,7 +118,7 @@ tlbtab:
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*/
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#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
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#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
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#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
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#define TLB02 TLB2(AC_RWX | SA_IG)
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.globl reconfig_tlb0
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reconfig_tlb0:
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@ -41,7 +41,7 @@
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tlbtab:
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tlbtab_start
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tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
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tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
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/*
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* TLB entries for SDRAM are not needed on this platform.
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@ -49,9 +49,9 @@ tlbtab:
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* routine.
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*/
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tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
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tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
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tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
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tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
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tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG)
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tlbtab_end
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@ -51,7 +51,7 @@ tlbtabA:
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* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
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* speed up boot process. It is patched after relocation to enable SA_I
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*/
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tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
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tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
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/*
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* TLB entries for SDRAM are not needed on this platform.
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@ -59,20 +59,20 @@ tlbtabA:
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* routine.
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*/
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tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
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tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
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tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
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tlbtab_end
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/**************************************************************************
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@ -91,7 +91,7 @@ tlbtabB:
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* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
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* speed up boot process. It is patched after relocation to enable SA_I
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*/
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tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
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tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
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/*
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* TLB entries for SDRAM are not needed on this platform.
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@ -99,20 +99,20 @@ tlbtabB:
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* routine.
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*/
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tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
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tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
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tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I)
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tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
|
||||
|
||||
tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
|
||||
tlbtab_end
|
||||
|
||||
@ -48,13 +48,13 @@ tlbtab:
|
||||
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_R|AC_W|AC_X|SA_G)
|
||||
tlbentry(0xfff00000, SZ_1M, 0xfff00000, 1, AC_RWX | SA_G)
|
||||
|
||||
tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(0xffc00000, SZ_1M, 0xffc00000, 1, AC_RWX | SA_IG)
|
||||
tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_RWX | SA_IG)
|
||||
tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_RWX | SA_IG)
|
||||
tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_RWX | SA_IG)
|
||||
tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_RW | SA_IG)
|
||||
|
||||
/*
|
||||
* TLB entries for SDRAM are not needed on this platform.
|
||||
@ -63,12 +63,12 @@ tlbtab:
|
||||
*/
|
||||
|
||||
/* internal ram (l2 cache) */
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_I)
|
||||
|
||||
/* peripherals at f0000000 */
|
||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_RW | SA_IG)
|
||||
|
||||
/* PCI */
|
||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_RW | SA_IG)
|
||||
tlbtab_end
|
||||
|
||||
@ -41,7 +41,7 @@
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
|
||||
tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
|
||||
|
||||
/*
|
||||
* TLB entries for SDRAM are not needed on this platform.
|
||||
@ -49,9 +49,9 @@ tlbtab:
|
||||
* routine.
|
||||
*/
|
||||
|
||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
|
||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
|
||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG)
|
||||
tlbtab_end
|
||||
|
||||
@ -45,7 +45,7 @@ tlbtab:
|
||||
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
|
||||
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
|
||||
|
||||
/*
|
||||
* TLB entries for SDRAM are not needed on this platform.
|
||||
@ -54,24 +54,24 @@ tlbtab:
|
||||
*/
|
||||
|
||||
/* Although 512 KB, map 256k at a time */
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_RWX | SA_I)
|
||||
|
||||
tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
|
||||
|
||||
/*
|
||||
* Peripheral base
|
||||
*/
|
||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_RW | SA_IG)
|
||||
|
||||
tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_RW | SA_IG)
|
||||
|
||||
tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_RW | SA_IG)
|
||||
|
||||
tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_RW | SA_IG)
|
||||
tlbtab_end
|
||||
|
||||
@ -41,7 +41,7 @@ tlbtab:
|
||||
tlbtab_start
|
||||
|
||||
/* vxWorks needs this as first entry for the Machine Check interrupt */
|
||||
tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
|
||||
|
||||
/*
|
||||
* The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
|
||||
@ -51,49 +51,49 @@ tlbtab:
|
||||
#ifndef CONFIG_SYS_RAMBOOT
|
||||
/* TLB-entry for DDR SDRAM (Up to 2GB) */
|
||||
#ifdef CONFIG_4xx_DCACHE
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_G)
|
||||
#else
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
|
||||
#endif
|
||||
#endif /* CONFIG_SYS_RAMBOOT */
|
||||
|
||||
/* TLB-entry for EBC */
|
||||
tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_RWX | SA_IG )
|
||||
|
||||
/* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
|
||||
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
|
||||
#else
|
||||
tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
|
||||
tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
|
||||
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
|
||||
#endif
|
||||
|
||||
/* TLB-entry for PCI Memory */
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
|
||||
|
||||
/* TLB-entry for NAND */
|
||||
tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
|
||||
|
||||
/* TLB-entry for Internal Registers & OCM */
|
||||
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
|
||||
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
|
||||
|
||||
/*TLB-entry PCI registers*/
|
||||
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
|
||||
|
||||
/* TLB-entry for peripherals */
|
||||
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
|
||||
|
||||
/* TLB-entry PCI IO Space - from sr@denx.de */
|
||||
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
|
||||
|
||||
tlbtab_end
|
||||
|
||||
@ -104,7 +104,7 @@ tlbtab:
|
||||
*/
|
||||
#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
|
||||
#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
|
||||
#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
#define TLB02 TLB2(AC_RWX | SA_IG)
|
||||
|
||||
.globl reconfig_tlb0
|
||||
reconfig_tlb0:
|
||||
|
||||
@ -22,56 +22,9 @@
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
|
||||
/* General */
|
||||
#define TLB_VALID 0x00000200
|
||||
#define _256M 0x10000000
|
||||
|
||||
/* Supported page sizes */
|
||||
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
#define SZ_64K 0x00000030
|
||||
#define SZ_256K 0x00000040
|
||||
#define SZ_1M 0x00000050
|
||||
#define SZ_8M 0x00000060
|
||||
#define SZ_16M 0x00000070
|
||||
#define SZ_256M 0x00000090
|
||||
|
||||
/* Storage attributes */
|
||||
#define SA_W 0x00000800 /* Write-through */
|
||||
#define SA_I 0x00000400 /* Caching inhibited */
|
||||
#define SA_M 0x00000200 /* Memory coherence */
|
||||
#define SA_G 0x00000100 /* Guarded */
|
||||
#define SA_E 0x00000080 /* Endian */
|
||||
|
||||
/* Access control */
|
||||
#define AC_X 0x00000024 /* Execute */
|
||||
#define AC_W 0x00000012 /* Write */
|
||||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
||||
#define TLB2(a) ( (a)&0x00000fbf )
|
||||
|
||||
#define tlbtab_start\
|
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\
|
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
@ -88,10 +41,10 @@
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
|
||||
tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
|
||||
tlbtab_end
|
||||
|
||||
@ -20,56 +20,9 @@
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
|
||||
/* General */
|
||||
#define TLB_VALID 0x00000200
|
||||
|
||||
/* Supported page sizes */
|
||||
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
#define SZ_64K 0x00000030
|
||||
#define SZ_256K 0x00000040
|
||||
#define SZ_1M 0x00000050
|
||||
#define SZ_8M 0x00000060
|
||||
#define SZ_16M 0x00000070
|
||||
#define SZ_256M 0x00000090
|
||||
|
||||
/* Storage attributes */
|
||||
#define SA_W 0x00000800 /* Write-through */
|
||||
#define SA_I 0x00000400 /* Caching inhibited */
|
||||
#define SA_M 0x00000200 /* Memory coherence */
|
||||
#define SA_G 0x00000100 /* Guarded */
|
||||
#define SA_E 0x00000080 /* Endian */
|
||||
|
||||
/* Access control */
|
||||
#define AC_X 0x00000024 /* Execute */
|
||||
#define AC_W 0x00000012 /* Write */
|
||||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
||||
#define TLB2(a) ( (a)&0x00000fbf )
|
||||
|
||||
#define tlbtab_start\
|
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\
|
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
@ -91,22 +44,22 @@ tlbtab:
|
||||
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
|
||||
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/)
|
||||
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
|
||||
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
|
||||
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I )
|
||||
|
||||
/* PCI */
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG )
|
||||
|
||||
/* USB 2.0 Device */
|
||||
tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG )
|
||||
|
||||
tlbtab_end
|
||||
|
||||
@ -51,7 +51,7 @@ tlbtabA:
|
||||
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
|
||||
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
|
||||
|
||||
/*
|
||||
* TLB entries for SDRAM are not needed on this platform.
|
||||
@ -59,23 +59,23 @@ tlbtabA:
|
||||
* routine.
|
||||
*/
|
||||
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
|
||||
tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
|
||||
tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
|
||||
|
||||
tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
|
||||
|
||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG)
|
||||
|
||||
tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG)
|
||||
tlbtab_end
|
||||
|
||||
/**************************************************************************
|
||||
@ -94,7 +94,7 @@ tlbtabB:
|
||||
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_R|AC_W|AC_X|SA_G)
|
||||
tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G)
|
||||
|
||||
/*
|
||||
* TLB entries for SDRAM are not needed on this platform.
|
||||
@ -102,20 +102,20 @@ tlbtabB:
|
||||
* routine.
|
||||
*/
|
||||
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
|
||||
tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I)
|
||||
tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_RW | SA_I)
|
||||
|
||||
tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_RWX | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG)
|
||||
|
||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG)
|
||||
|
||||
tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG)
|
||||
tlbtab_end
|
||||
|
||||
@ -44,38 +44,38 @@ tlbtab:
|
||||
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
|
||||
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
|
||||
|
||||
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
|
||||
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
|
||||
#endif
|
||||
|
||||
/* TLB-entry for PCI Memory */
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
|
||||
|
||||
/* TLB-entry for PCI IO */
|
||||
tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_RW | SA_IG )
|
||||
|
||||
/* TLB-entries for EBC: CPLD, DUMEM, DUIO */
|
||||
tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_RWX | SA_IG )
|
||||
|
||||
/* TLB-entry for NAND */
|
||||
tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_RWX | SA_IG )
|
||||
|
||||
/* TLB-entry for Internal Registers & OCM */
|
||||
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
|
||||
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
|
||||
|
||||
/* TLB-entry PCI registers */
|
||||
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
|
||||
|
||||
/* TLB-entry for peripherals */
|
||||
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
|
||||
|
||||
tlbtab_end
|
||||
|
||||
@ -44,23 +44,23 @@ tlbtab:
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
|
||||
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
|
||||
#else
|
||||
tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
|
||||
tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
|
||||
#endif
|
||||
|
||||
/* TLB entries for DDR2 SDRAM are generated dynamically */
|
||||
|
||||
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
|
||||
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
|
||||
#endif
|
||||
|
||||
/* TLB-entry for PCI Memory */
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
|
||||
|
||||
/* TLB-entries for EBC */
|
||||
/* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
|
||||
@ -68,22 +68,22 @@ tlbtab:
|
||||
* This dummy entry is only for convinience in order not to modify the
|
||||
* amount of entries. Currently OS/9 relies on this :-)
|
||||
*/
|
||||
tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG )
|
||||
|
||||
/* TLB-entry for NAND */
|
||||
tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
|
||||
|
||||
/* TLB-entry for Internal Registers & OCM */
|
||||
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
|
||||
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
|
||||
|
||||
/*TLB-entry PCI registers*/
|
||||
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
|
||||
|
||||
/* TLB-entry for peripherals */
|
||||
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
|
||||
|
||||
/* TLB-entry PCI IO space */
|
||||
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
|
||||
|
||||
/* TODO: what about high IO space */
|
||||
tlbtab_end
|
||||
@ -95,7 +95,7 @@ tlbtab:
|
||||
*/
|
||||
#define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
|
||||
#define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
|
||||
#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
#define TLB02 TLB2(AC_RWX | SA_IG)
|
||||
|
||||
.globl reconfig_tlb0
|
||||
reconfig_tlb0:
|
||||
|
||||
@ -51,25 +51,25 @@ tlbtab:
|
||||
* the speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR,
|
||||
0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
|
||||
0, AC_RWX | SA_G/*|SA_I*/)
|
||||
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
0, AC_R|AC_W|AC_X|SA_G )
|
||||
0, AC_RWX | SA_G )
|
||||
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE,
|
||||
0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE,
|
||||
0, AC_R|AC_W|SA_G|SA_I )
|
||||
0, AC_RW | SA_IG )
|
||||
|
||||
/* PCI */
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE,
|
||||
0, AC_R|AC_W|SA_G|SA_I )
|
||||
0, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1,
|
||||
0, AC_R|AC_W|SA_G|SA_I )
|
||||
0, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2,
|
||||
0, AC_R|AC_W|SA_G|SA_I )
|
||||
0, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3,
|
||||
0, AC_R|AC_W|SA_G|SA_I )
|
||||
0, AC_RW | SA_IG )
|
||||
|
||||
tlbtab_end
|
||||
|
||||
@ -51,7 +51,7 @@ tlbtab:
|
||||
* enable SA_I
|
||||
*/
|
||||
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
|
||||
4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
|
||||
4, AC_RWX | SA_G) /* TLB 0 */
|
||||
|
||||
/*
|
||||
* TLB entries for SDRAM are not needed on this platform.
|
||||
@ -62,36 +62,36 @@ tlbtab:
|
||||
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
0, AC_R|AC_W|AC_X|SA_G)
|
||||
0, AC_RWX | SA_G)
|
||||
#endif
|
||||
|
||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
|
||||
AC_R|AC_W|SA_G|SA_I)
|
||||
AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC,
|
||||
AC_R|AC_W|SA_G|SA_I)
|
||||
AC_RW | SA_IG)
|
||||
|
||||
/* TLB-entry for NVRAM */
|
||||
tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4,
|
||||
AC_R|AC_W|SA_G|SA_I)
|
||||
AC_RW | SA_IG)
|
||||
|
||||
/* TLB-entry for UART */
|
||||
tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4,
|
||||
AC_R|AC_W|SA_G|SA_I)
|
||||
AC_RW | SA_IG)
|
||||
|
||||
/* TLB-entry for IO */
|
||||
tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4,
|
||||
AC_R|AC_W|SA_G|SA_I)
|
||||
AC_RW | SA_IG)
|
||||
|
||||
/* TLB-entry for OCM */
|
||||
tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
|
||||
AC_R|AC_W|AC_X|SA_I)
|
||||
AC_RWX | SA_I)
|
||||
|
||||
/* TLB-entry for Local Configuration registers => peripherals */
|
||||
tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS,
|
||||
4, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
4, AC_RWX | SA_IG)
|
||||
|
||||
/* AHB: Internal USB Peripherals (USB, SATA) */
|
||||
tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4,
|
||||
AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
AC_RWX | SA_IG)
|
||||
|
||||
tlbtab_end
|
||||
|
||||
@ -43,7 +43,7 @@ tlbtab:
|
||||
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_R|AC_W|AC_X|SA_G )
|
||||
tlbentry( 0xF0000000, SZ_256M, 0xF0000000, 1, AC_RWX | SA_G )
|
||||
|
||||
/*
|
||||
* TLB entries for SDRAM are not needed on this platform. They are
|
||||
@ -53,37 +53,37 @@ tlbtab:
|
||||
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0,
|
||||
AC_R|AC_W|AC_X|SA_G )
|
||||
AC_RWX | SA_G )
|
||||
#endif
|
||||
|
||||
/* TLB-entry for PCI Memory */
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M,
|
||||
CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_RW | SA_IG )
|
||||
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M,
|
||||
CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_RW | SA_IG )
|
||||
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M,
|
||||
CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_RW | SA_IG )
|
||||
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M,
|
||||
CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_RW | SA_IG )
|
||||
|
||||
/* TLB-entry for EBC */
|
||||
tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RW | SA_IG )
|
||||
|
||||
/* TLB-entry for Internal Registers & OCM */
|
||||
/* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
|
||||
tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_R|AC_W|AC_X|SA_I )
|
||||
tlbentry( 0xE0000000, SZ_16M, 0xE0000000, 0, AC_RWX | SA_I )
|
||||
|
||||
/*TLB-entry PCI registers*/
|
||||
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RW | SA_IG )
|
||||
|
||||
/* TLB-entry for peripherals */
|
||||
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RW | SA_IG)
|
||||
|
||||
/* TLB-entry PCI IO Space - from sr@denx.de */
|
||||
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RW | SA_IG)
|
||||
|
||||
tlbtab_end
|
||||
|
||||
|
||||
@ -47,7 +47,7 @@ tlbtab:
|
||||
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G)
|
||||
tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G)
|
||||
|
||||
/*
|
||||
* TLB entries for SDRAM are not needed on this platform.
|
||||
@ -57,34 +57,34 @@ tlbtab:
|
||||
|
||||
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
|
||||
tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
|
||||
#endif
|
||||
|
||||
/* TLB-entry for PCI Memory */
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG)
|
||||
|
||||
/* TLB-entry for the FPGA Chip select 2 */
|
||||
tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
|
||||
tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_RWX | SA_I|SA_G)
|
||||
|
||||
/* TLB-entry for the FPGA Chip select 3 */
|
||||
tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_R|AC_W|AC_X|SA_I|SA_G)
|
||||
tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_RWX | SA_I|SA_G)
|
||||
|
||||
/* TLB-entry for the LIME Controller */
|
||||
tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
|
||||
tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
|
||||
tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
|
||||
tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
|
||||
tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_RWX | SA_I|SA_G)
|
||||
tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_RWX | SA_I|SA_G)
|
||||
tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_RWX | SA_I|SA_G)
|
||||
tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_RWX | SA_I|SA_G)
|
||||
|
||||
/* TLB-entry for Internal Registers & OCM */
|
||||
tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I)
|
||||
tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I)
|
||||
|
||||
/*TLB-entry PCI registers*/
|
||||
tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG)
|
||||
|
||||
/* TLB-entry for peripherals */
|
||||
tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
|
||||
|
||||
tlbtab_end
|
||||
|
||||
@ -40,13 +40,13 @@ tlbtab:
|
||||
tlbtab_start
|
||||
|
||||
/* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */
|
||||
tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( 0x40000000, SZ_256M, 0, 0, AC_RWX | SA_IG )
|
||||
/* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0,
|
||||
AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
AC_RWX | SA_IG )
|
||||
|
||||
/* TLB#2: TLB-entry for EBC */
|
||||
tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( 0x80000000, SZ_256M, 0x80000000, 1, AC_RWX | SA_IG)
|
||||
|
||||
/*
|
||||
* TLB#3: BOOT_CS (FLASH) must be forth. Before relocation SA_I can be
|
||||
@ -54,7 +54,7 @@ tlbtab:
|
||||
* to enable SA_I
|
||||
*/
|
||||
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_1M, CONFIG_SYS_BOOT_BASE_ADDR, 1,
|
||||
AC_R|AC_W|AC_X|SA_G)
|
||||
AC_RWX | SA_G)
|
||||
|
||||
/*
|
||||
* TLB entries for SDRAM are not needed on this platform.
|
||||
@ -64,43 +64,43 @@ tlbtab:
|
||||
|
||||
/* TLB#4: */
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1,
|
||||
AC_R|AC_W|SA_G|SA_I )
|
||||
AC_RW | SA_IG )
|
||||
/* TLB#5: */
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1,
|
||||
AC_R|AC_W|SA_G|SA_I )
|
||||
AC_RW | SA_IG )
|
||||
/* TLB#6: */
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1,
|
||||
AC_R|AC_W|SA_G|SA_I )
|
||||
AC_RW | SA_IG )
|
||||
|
||||
/* TLB-entry for Internal Registers & OCM */
|
||||
/* TLB#7: */
|
||||
tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,
|
||||
AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
AC_RWX | SA_IG )
|
||||
|
||||
/*TLB-entry PCI registers*/
|
||||
/* TLB#8: */
|
||||
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
|
||||
|
||||
/* TLB-entry for peripherals */
|
||||
/* TLB#9: */
|
||||
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
|
||||
|
||||
/* CAN */
|
||||
/* TLB#10: */
|
||||
tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_RWX | SA_IG )
|
||||
|
||||
/* TLB#11: CPLD and IMC-Standard 32 MB */
|
||||
tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_RWX | SA_IG )
|
||||
|
||||
/* TLB#12: */
|
||||
tlbentry( CONFIG_SYS_CS_2 + 0x1000000, SZ_16M, CONFIG_SYS_CS_2 + 0x1000000, 1,
|
||||
AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
AC_RWX | SA_IG )
|
||||
|
||||
/* IMC-Fast 32 MB */
|
||||
/* TLB#13: */
|
||||
tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_RWX | SA_IG )
|
||||
/* TLB#14: */
|
||||
tlbentry( CONFIG_SYS_CS_3 + 0x1000000, SZ_16M, CONFIG_SYS_CS_3, 1,
|
||||
AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
AC_RWX | SA_IG )
|
||||
|
||||
tlbtab_end
|
||||
|
||||
@ -22,56 +22,9 @@
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
|
||||
/* General */
|
||||
#define TLB_VALID 0x00000200
|
||||
|
||||
/* Supported page sizes */
|
||||
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
#define SZ_64K 0x00000030
|
||||
#define SZ_256K 0x00000040
|
||||
#define SZ_1M 0x00000050
|
||||
#define SZ_8M 0x00000060
|
||||
#define SZ_16M 0x00000070
|
||||
#define SZ_256M 0x00000090
|
||||
|
||||
/* Storage attributes */
|
||||
#define SA_W 0x00000800 /* Write-through */
|
||||
#define SA_I 0x00000400 /* Caching inhibited */
|
||||
#define SA_M 0x00000200 /* Memory coherence */
|
||||
#define SA_G 0x00000100 /* Guarded */
|
||||
#define SA_E 0x00000080 /* Endian */
|
||||
|
||||
/* Access control */
|
||||
#define AC_X 0x00000024 /* Execute */
|
||||
#define AC_W 0x00000012 /* Write */
|
||||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
||||
#define TLB2(a) ( (a)&0x00000fbf )
|
||||
|
||||
#define tlbtab_start\
|
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\
|
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
@ -93,10 +46,10 @@ tlbtab:
|
||||
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
|
||||
tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G/*|SA_I*/)
|
||||
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
|
||||
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
|
||||
|
||||
/*
|
||||
* TLB entries for SDRAM are not needed on this platform.
|
||||
@ -104,15 +57,15 @@ tlbtab:
|
||||
* routine.
|
||||
*/
|
||||
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG )
|
||||
|
||||
/* PCI */
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG )
|
||||
|
||||
/* USB 2.0 Device */
|
||||
tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_RW | SA_IG )
|
||||
|
||||
tlbtab_end
|
||||
|
||||
@ -22,54 +22,9 @@
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
|
||||
/* General */
|
||||
#define TLB_VALID 0x00000200
|
||||
|
||||
/* Supported page sizes */
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
#define SZ_64K 0x00000030
|
||||
#define SZ_256K 0x00000040
|
||||
#define SZ_1M 0x00000050
|
||||
#define SZ_16M 0x00000070
|
||||
#define SZ_256M 0x00000090
|
||||
|
||||
/* Storage attributes */
|
||||
#define SA_W 0x00000800 /* Write-through */
|
||||
#define SA_I 0x00000400 /* Caching inhibited */
|
||||
#define SA_M 0x00000200 /* Memory coherence */
|
||||
#define SA_G 0x00000100 /* Guarded */
|
||||
#define SA_E 0x00000080 /* Endian */
|
||||
|
||||
/* Access control */
|
||||
#define AC_X 0x00000024 /* Execute */
|
||||
#define AC_W 0x00000012 /* Write */
|
||||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
||||
#define TLB2(a) ( (a)&0x00000fbf )
|
||||
|
||||
#define tlbtab_start\
|
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\
|
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
@ -86,27 +41,27 @@
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbentry( 0xff000000, SZ_16M, 0xff000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
|
||||
tlbentry(0xff000000, SZ_16M, 0xff000000, 1, AC_RWX | SA_IG )
|
||||
tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX)
|
||||
tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX)
|
||||
#ifdef CONFIG_4xx_DCACHE
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G)
|
||||
tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_G)
|
||||
#else
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_INIT_RAM_DCACHE
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
|
||||
tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
|
||||
#endif
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG)
|
||||
|
||||
/* PCI */
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_RW | SA_IG)
|
||||
tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_RW | SA_IG)
|
||||
|
||||
/* NAND */
|
||||
tlbentry( CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry(CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_RWX | SA_IG)
|
||||
tlbtab_end
|
||||
|
||||
@ -24,55 +24,9 @@
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
|
||||
/* General */
|
||||
#define TLB_VALID 0x00000200
|
||||
|
||||
/* Supported page sizes */
|
||||
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
#define SZ_64K 0x00000030
|
||||
#define SZ_256K 0x00000040
|
||||
#define SZ_1M 0x00000050
|
||||
#define SZ_16M 0x00000070
|
||||
#define SZ_256M 0x00000090
|
||||
|
||||
/* Storage attributes */
|
||||
#define SA_W 0x00000800 /* Write-through */
|
||||
#define SA_I 0x00000400 /* Caching inhibited */
|
||||
#define SA_M 0x00000200 /* Memory coherence */
|
||||
#define SA_G 0x00000100 /* Guarded */
|
||||
#define SA_E 0x00000080 /* Endian */
|
||||
|
||||
/* Access control */
|
||||
#define AC_X 0x00000024 /* Execute */
|
||||
#define AC_W 0x00000012 /* Write */
|
||||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
||||
#define TLB2(a) ( (a)&0x00000fbf )
|
||||
|
||||
#define tlbtab_start\
|
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\
|
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
@ -89,11 +43,11 @@
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
|
||||
tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_RWX )
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_RWX )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
|
||||
tlbtab_end
|
||||
|
||||
@ -24,55 +24,9 @@
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
|
||||
/* General */
|
||||
#define TLB_VALID 0x00000200
|
||||
|
||||
/* Supported page sizes */
|
||||
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
#define SZ_64K 0x00000030
|
||||
#define SZ_256K 0x00000040
|
||||
#define SZ_1M 0x00000050
|
||||
#define SZ_16M 0x00000070
|
||||
#define SZ_256M 0x00000090
|
||||
|
||||
/* Storage attributes */
|
||||
#define SA_W 0x00000800 /* Write-through */
|
||||
#define SA_I 0x00000400 /* Caching inhibited */
|
||||
#define SA_M 0x00000200 /* Memory coherence */
|
||||
#define SA_G 0x00000100 /* Guarded */
|
||||
#define SA_E 0x00000080 /* Endian */
|
||||
|
||||
/* Access control */
|
||||
#define AC_X 0x00000024 /* Execute */
|
||||
#define AC_W 0x00000012 /* Write */
|
||||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
||||
#define TLB2(a) ( (a)&0x00000fbf )
|
||||
|
||||
#define tlbtab_start\
|
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\
|
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
@ -89,13 +43,13 @@
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
|
||||
tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
|
||||
tlbtab_end
|
||||
|
||||
@ -22,55 +22,9 @@
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
|
||||
/* General */
|
||||
#define TLB_VALID 0x00000200
|
||||
|
||||
/* Supported page sizes */
|
||||
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
#define SZ_64K 0x00000030
|
||||
#define SZ_256K 0x00000040
|
||||
#define SZ_1M 0x00000050
|
||||
#define SZ_16M 0x00000070
|
||||
#define SZ_256M 0x00000090
|
||||
|
||||
/* Storage attributes */
|
||||
#define SA_W 0x00000800 /* Write-through */
|
||||
#define SA_I 0x00000400 /* Caching inhibited */
|
||||
#define SA_M 0x00000200 /* Memory coherence */
|
||||
#define SA_G 0x00000100 /* Guarded */
|
||||
#define SA_E 0x00000080 /* Endian */
|
||||
|
||||
/* Access control */
|
||||
#define AC_X 0x00000024 /* Execute */
|
||||
#define AC_W 0x00000012 /* Write */
|
||||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
||||
#define TLB2(a) ( (a)&0x00000fbf )
|
||||
|
||||
#define tlbtab_start\
|
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\
|
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
@ -87,13 +41,13 @@
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
|
||||
tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
|
||||
tlbtab_end
|
||||
|
||||
@ -21,53 +21,9 @@
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <asm/mmu.h>
|
||||
#include <config.h>
|
||||
|
||||
/* General */
|
||||
#define TLB_VALID 0x00000200
|
||||
|
||||
/* Supported page sizes */
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
#define SZ_64K 0x00000030
|
||||
#define SZ_256K 0x00000040
|
||||
#define SZ_1M 0x00000050
|
||||
#define SZ_16M 0x00000070
|
||||
#define SZ_256M 0x00000090
|
||||
|
||||
/* Storage attributes */
|
||||
#define SA_W 0x00000800 /* Write-through */
|
||||
#define SA_I 0x00000400 /* Caching inhibited */
|
||||
#define SA_M 0x00000200 /* Memory coherence */
|
||||
#define SA_G 0x00000100 /* Guarded */
|
||||
#define SA_E 0x00000080 /* Endian */
|
||||
|
||||
/* Access control */
|
||||
#define AC_X 0x00000024 /* Execute */
|
||||
#define AC_W 0x00000012 /* Write */
|
||||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
|
||||
#define TLB1(rpn,erpn) (((rpn)&0xfffffc00) | (erpn))
|
||||
#define TLB2(a) ((a)&0x00000fbf)
|
||||
|
||||
#define tlbtab_start \
|
||||
mflr r1; \
|
||||
bl 0f;
|
||||
|
||||
#define tlbtab_end \
|
||||
.long 0, 0, 0; \
|
||||
0: mflr r0; \
|
||||
mtlr r1; \
|
||||
blr;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
|
||||
/*
|
||||
* TLB TABLE
|
||||
*
|
||||
@ -83,11 +39,11 @@
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
|
||||
tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
|
||||
tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
|
||||
tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
|
||||
tlbtab_end
|
||||
|
||||
Loading…
Reference in New Issue
Block a user