Bin Meng 85c714d8dc riscv: Adjust board_get_usable_ram_top() for 32-bit ... When testing QEMU RISC-V 'virt' machine with a 2 GiB memory configuration, it was discovered gd->ram_top is assigned to value zero in setup_dest_addr(). While gd->ram_top should not be declared as type `unsigned long`, which will be updated in a future patch, the current logic in board_get_usable_ram_top() can be updated to cover both 64-bit and 32-bit RISC-V. Signed-off-by: Bin Meng <bin.meng@windriver.com>		2021-02-03 03:38:41 -07:00
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cache.c	riscv: fu540: Use correct API to get L2 cache controller base address	2020-08-25 09:33:16 +08:00
cpu.c	riscv: cpu: fu540: Add support for cpu fu540	2020-06-04 09:44:09 +08:00
dram.c	riscv: Adjust board_get_usable_ram_top() for 32-bit	2021-02-03 03:38:41 -07:00
Kconfig	riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller	2020-11-28 08:30:41 +01:00
Makefile	riscv: sifive: fu540: enable all cache ways from U-Boot proper	2020-07-03 15:09:06 +08:00
spl.c	riscv: sifive/fu540: spl: Rename soc_spl_init()	2020-08-14 14:38:53 +08:00