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riscv: Adjust board_get_usable_ram_top() for 32-bit

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When testing QEMU RISC-V 'virt' machine with a 2 GiB memory
configuration, it was discovered gd->ram_top is assigned to
value zero in setup_dest_addr().

While gd->ram_top should not be declared as type `unsigned long`,
which will be updated in a future patch, the current logic in
board_get_usable_ram_top() can be updated to cover both 64-bit
and 32-bit RISC-V.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
This commit is contained in:
Bin Meng 2021-01-31 20:35:57 +08:00 committed by Simon Glass
parent 7a3c628c43
commit 85c714d8dc
2 changed files with 6 additions and 8 deletions
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7
arch/riscv/cpu/fu540/dram.c
View File

@ -22,7 +22,6 @@ int dram_init_banksize(void)
ulong board_get_usable_ram_top(ulong total_size)
{
#ifdef CONFIG_64BIT
/*
* Ensure that we run from first 4GB so that all
* addresses used by U-Boot are 32bit addresses.
@ -31,8 +30,8 @@ ulong board_get_usable_ram_top(ulong total_size)
* devices work fine because DMA mapping APIs will
* provide 32bit DMA addresses only.
*/
if (gd->ram_top > SZ_4G)
return SZ_4G;
#endif
if (gd->ram_top >= SZ_4G)
return SZ_4G - 1;
return gd->ram_top;
}

7
arch/riscv/cpu/generic/dram.c
View File

@ -22,7 +22,6 @@ int dram_init_banksize(void)
ulong board_get_usable_ram_top(ulong total_size)
{
#ifdef CONFIG_64BIT
/*
* Ensure that we run from first 4GB so that all
* addresses used by U-Boot are 32bit addresses.
@ -31,8 +30,8 @@ ulong board_get_usable_ram_top(ulong total_size)
* devices work fine because DMA mapping APIs will
* provide 32bit DMA addresses only.
*/
if (gd->ram_top > SZ_4G)
return SZ_4G;
#endif
if (gd->ram_top >= SZ_4G)
return SZ_4G - 1;
return gd->ram_top;
}