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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 18:09:03 +09:00
![Sriram Dash](/assets/img/avatar_default.png)
The function fdt_fixup_dr_usb is specific to fsl/nxp. So, make the function name explicit and rename fdt_fixup_dr_usb into fsl_fdt_fixup_dr_usb. Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
242 lines
5.4 KiB
C
242 lines
5.4 KiB
C
/*
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* Copyright 2011,2012 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <linux/compiler.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_liodn.h>
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#include <fm_eth.h>
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extern void pci_of_setup(void *blob, bd_t *bd);
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#include "cpld.h"
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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u8 sw;
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struct cpu_type *cpu = gd->arch.cpu;
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unsigned int i;
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printf("Board: %sRDB, ", cpu->name);
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printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver),
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CPLD_READ(cpld_ver_sub));
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sw = CPLD_READ(fbank_sel);
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printf("vBank: %d\n", sw & 0x1);
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/*
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* Display the actual SERDES reference clocks as configured by the
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* dip switches on the board. Note that the SWx registers could
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* technically be set to force the reference clocks to match the
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* values that the SERDES expects (or vice versa). For now, however,
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* we just display both values and hope the user notices when they
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* don't match.
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*/
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puts("SERDES Reference Clocks: ");
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sw = in_8(&CPLD_SW(2)) >> 2;
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for (i = 0; i < 2; i++) {
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static const char * const freq[][3] = {{"0", "100", "125"},
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{"100", "156.25", "125"}
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};
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unsigned int clock = (sw >> (2 * i)) & 3;
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printf("Bank%u=%sMhz ", i+1, freq[i][clock]);
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}
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puts("\n");
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return 0;
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}
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int board_early_init_f(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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/* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */
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setbits_be32(&gur->ddrclkdr, 0x000f000f);
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return 0;
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}
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#define CPLD_LANE_A_SEL 0x1
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#define CPLD_LANE_G_SEL 0x2
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#define CPLD_LANE_C_SEL 0x4
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#define CPLD_LANE_D_SEL 0x8
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void board_config_lanes_mux(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
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FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
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u8 mux = 0;
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switch (srds_prtcl) {
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case 0x2:
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case 0x5:
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case 0x9:
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case 0xa:
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case 0xf:
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break;
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case 0x8:
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mux |= CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
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break;
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case 0x14:
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mux |= CPLD_LANE_A_SEL;
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break;
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case 0x17:
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mux |= CPLD_LANE_G_SEL;
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break;
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case 0x16:
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case 0x19:
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case 0x1a:
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mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
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break;
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case 0x1c:
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mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
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break;
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default:
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printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
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break;
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}
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CPLD_WRITE(serdes_mux, mux);
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}
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 2; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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board_config_lanes_mux();
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return 0;
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}
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unsigned long get_board_sys_clk(unsigned long dummy)
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{
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u8 sysclk_conf = CPLD_READ(sysclk_sw1);
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switch (sysclk_conf & 0x7) {
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case CPLD_SYSCLK_83:
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return 83333333;
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case CPLD_SYSCLK_100:
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return 100000000;
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default:
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return 66666666;
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}
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}
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#define NUM_SRDS_BANKS 2
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int misc_init_r(void)
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{
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serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
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u32 actual[NUM_SRDS_BANKS];
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unsigned int i;
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u8 sw;
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static const int freq[][3] = {
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{0, SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_125},
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{SRDS_PLLCR0_RFCK_SEL_100, SRDS_PLLCR0_RFCK_SEL_156_25,
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SRDS_PLLCR0_RFCK_SEL_125}
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};
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sw = in_8(&CPLD_SW(2)) >> 2;
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for (i = 0; i < NUM_SRDS_BANKS; i++) {
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unsigned int clock = (sw >> (2 * i)) & 3;
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if (clock == 0x3) {
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printf("Warning: SDREFCLK%u switch setting of '11' is "
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"unsupported\n", i + 1);
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break;
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}
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if (i == 0 && clock == 0)
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puts("Warning: SDREFCLK1 switch setting of"
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"'00' is unsupported\n");
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else
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actual[i] = freq[i][clock];
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/*
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* PC board uses a different CPLD with PB board, this CPLD
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* has cpld_ver_sub = 1, and pcba_ver = 5. But CPLD on PB
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* board has cpld_ver_sub = 0, and pcba_ver = 4.
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*/
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if ((i == 1) && (CPLD_READ(cpld_ver_sub) == 1) &&
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(CPLD_READ(pcba_ver) == 5)) {
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/* PC board bank2 frequency */
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actual[i] = freq[i-1][clock];
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}
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}
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for (i = 0; i < NUM_SRDS_BANKS; i++) {
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u32 expected = in_be32(®s->bank[i].pllcr0);
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expected &= SRDS_PLLCR0_RFCK_SEL_MASK;
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if (expected != actual[i]) {
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printf("Warning: SERDES bank %u expects reference clock"
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" %sMHz, but actual is %sMHz\n", i + 1,
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serdes_clock_to_string(expected),
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serdes_clock_to_string(actual[i]));
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}
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}
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return 0;
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
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fsl_fdt_fixup_dr_usb(blob, bd);
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#endif
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#ifdef CONFIG_PCI
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pci_of_setup(blob, bd);
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#endif
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fdt_fixup_liodn(blob);
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_fman_ethernet(blob);
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#endif
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return 0;
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}
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