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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 18:09:03 +09:00
![Sumit Garg](/assets/img/avatar_default.png)
Using changes in this patch we were able to reduce approx 10k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size: 1. Changes in board/freescale/ls1043ardb/Makefile to remove compilation of eth.c and cpld.c in case of SPL build. 2. Changes in board/freescale/ls1043ardb/ls1043ardb.c to keep only ddr_init and board_early_init_f funcations in case of SPL build. 3. Changes in ls1043a_common.h & ls1043ardb.h to remove driver specific macros due to which static data was being compiled in case of SPL build. 4. Disable MMC driver from bieng compiled in case of SPL NAND build and NAND driver from bieng compiled in case of SPL MMC build. 5. Remove I2C driver support from SPL in case of LS1043ARDB. Signed-off-by: Vinitha Pillai <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
220 lines
4.5 KiB
C
220 lines
4.5 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include <fdt_support.h>
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#include <hwconfig.h>
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#include <ahci.h>
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#include <mmc.h>
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#include <scsi.h>
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#include <fm_eth.h>
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#include <fsl_esdhc.h>
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#include <fsl_ifc.h>
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#include <fsl_sec.h>
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#include "cpld.h"
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#ifdef CONFIG_U_QE
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#include <fsl_qe.h>
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#endif
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#include <asm/arch/ppa.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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fsl_lsch2_early_init_f();
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return 0;
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}
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#ifndef CONFIG_SPL_BUILD
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int checkboard(void)
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{
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static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
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#ifndef CONFIG_SD_BOOT
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u8 cfg_rcw_src1, cfg_rcw_src2;
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u16 cfg_rcw_src;
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#endif
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u8 sd1refclk_sel;
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printf("Board: LS1043ARDB, boot from ");
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#ifdef CONFIG_SD_BOOT
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puts("SD\n");
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#else
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cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
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cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
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cpld_rev_bit(&cfg_rcw_src1);
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cfg_rcw_src = cfg_rcw_src1;
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cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
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if (cfg_rcw_src == 0x25)
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printf("vBank %d\n", CPLD_READ(vbank));
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else if (cfg_rcw_src == 0x106)
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puts("NAND\n");
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else
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printf("Invalid setting of SW4\n");
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#endif
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printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
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CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
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puts("SERDES Reference Clocks:\n");
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sd1refclk_sel = CPLD_READ(sd1refclk_sel);
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printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
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return 0;
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}
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int board_init(void)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
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erratum_a010315();
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#endif
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#ifdef CONFIG_FSL_IFC
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init_final_memctl_regs();
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#endif
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#ifdef CONFIG_SECURE_BOOT
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/* In case of Secure Boot, the IBR configures the SMMU
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* to allow only Secure transactions.
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* SMMU must be reset in bypass mode.
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* Set the ClientPD bit and Clear the USFCFG Bit
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*/
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u32 val;
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val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
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out_le32(SMMU_SCR0, val);
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val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
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out_le32(SMMU_NSCR0, val);
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#endif
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#ifdef CONFIG_FSL_CAAM
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sec_init();
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#endif
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#ifdef CONFIG_FSL_LS_PPA
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ppa_init();
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#endif
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#ifdef CONFIG_U_QE
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u_qe_init();
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#endif
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/* invert AQR105 IRQ pins polarity */
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out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
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return 0;
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}
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int config_board_mux(void)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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u32 usb_pwrfault;
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if (hwconfig("qe-hdlc")) {
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out_be32(&scfg->rcwpmuxcr0,
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(in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
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printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
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in_be32(&scfg->rcwpmuxcr0));
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} else {
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#ifdef CONFIG_HAS_FSL_XHCI_USB
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out_be32(&scfg->rcwpmuxcr0, 0x3333);
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out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
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usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
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SCFG_USBPWRFAULT_USB3_SHIFT) |
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(SCFG_USBPWRFAULT_DEDICATED <<
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SCFG_USBPWRFAULT_USB2_SHIFT) |
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(SCFG_USBPWRFAULT_SHARED <<
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SCFG_USBPWRFAULT_USB1_SHIFT);
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out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
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#endif
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}
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return 0;
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}
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#if defined(CONFIG_MISC_INIT_R)
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int misc_init_r(void)
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{
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config_board_mux();
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return 0;
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}
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#endif
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void fdt_del_qe(void *blob)
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{
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int nodeoff = 0;
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while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
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"fsl,qe")) >= 0) {
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fdt_del_node(blob, nodeoff);
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}
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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u64 base[CONFIG_NR_DRAM_BANKS];
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u64 size[CONFIG_NR_DRAM_BANKS];
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/* fixup DT for the two DDR banks */
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base[0] = gd->bd->bi_dram[0].start;
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size[0] = gd->bd->bi_dram[0].size;
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base[1] = gd->bd->bi_dram[1].start;
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size[1] = gd->bd->bi_dram[1].size;
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fdt_fixup_memory_banks(blob, base, size, 2);
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_fman_ethernet(blob);
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#endif
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/*
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* qe-hdlc and usb multi-use the pins,
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* when set hwconfig to qe-hdlc, delete usb node.
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*/
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if (hwconfig("qe-hdlc"))
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#ifdef CONFIG_HAS_FSL_XHCI_USB
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fdt_del_node_and_alias(blob, "usb1");
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#endif
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/*
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* qe just support qe-uart and qe-hdlc,
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* if qe-uart and qe-hdlc are not set in hwconfig,
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* delete qe node.
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*/
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if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
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fdt_del_qe(blob);
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return 0;
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}
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u8 flash_read8(void *addr)
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{
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return __raw_readb(addr + 1);
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}
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void flash_write16(u16 val, void *addr)
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{
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u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
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__raw_writew(shftval, addr);
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}
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u16 flash_read16(void *addr)
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{
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u16 val = __raw_readw(addr);
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return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
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}
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#endif
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