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https://github.com/brain-hackers/u-boot-brain
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0ea3671d35
Pin mux logic has 2 options in priority order, one is through RCW_SRC and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT to control the SPI muxing. But actually those are DSPI controller's pads instead of QSPI controller's, so this workaround allows RCW fields SPI_BASE and SPI_EXT to control relevant pads muxing. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> [York Sun: Reformatted commit message] Reviewed-by: York Sun <york.sun@nxp.com>
23 lines
554 B
Plaintext
23 lines
554 B
Plaintext
config ARCH_LS1012A
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bool "Freescale Layerscape LS1012A SoC"
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select SYS_FSL_MMDC
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select SYS_FSL_ERRATUM_A010315
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config ARCH_LS1043A
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bool "Freescale Layerscape LS1043A SoC"
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_ERRATUM_A010539
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config ARCH_LS1046A
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bool "Freescale Layerscape LS1046A SoC"
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select SYS_FSL_ERRATUM_A010539
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config SYS_FSL_MMDC
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bool "Freescale Multi Mode DDR Controller"
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config SYS_FSL_ERRATUM_A010315
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bool "Workaround for PCIe erratum A010315"
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config SYS_FSL_ERRATUM_A010539
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bool "Workaround for PIN MUX erratum A010539"
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