mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
8f74e659c4
Due to how the Makefile logic is we currently get DM_SPI support in SPL enabled by having DM_SPI enabled for full U-Boot but not having CONFIG_SPL_DM_SPI set. Add this missing option to boards that were inadvertently making use of it. Cc: Adam Ford <aford173@gmail.com> Cc: Akash Gajjar <akash@openedev.com> Cc: Anatolij Gustschin <agust@denx.de> Cc: Andy Yan <andy.yan@rock-chips.com> Cc: Anup Patel <anup.patel@wdc.com> Cc: Atish Patra <atish.patra@wdc.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Chee Hong Ang <chee.hong.ang@intel.com> Cc: Chin-Liang See <clsee@altera.com> Cc: Dalon Westergreen <dwesterg@gmail.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Hannes Schmelzer <hannes.schmelzer@br-automation.com> Cc: Heiko Schocher <hs@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Klaus Goger <klaus.goger@theobroma-systems.com> Cc: Levin Du <djw@t-chip.com.cn> Cc: Ley Foon Tan <ley.foon.tan@intel.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Luca Ceresoli <luca@lucaceresoli.net> Cc: Marek Vasut <marex@denx.de> Cc: Michal Simek <monstr@monstr.eu> Cc: Mike Looijmans <mike.looijmans@topic.nl> Cc: Nicolas Ferre <nicolas.ferre@microchip.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Pavel Machek <pavel@denx.de> Cc: Peter Robinson <pbrobinson@gmail.com> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefan Roese <sr@denx.de> Cc: Suniel Mahesh <sunil@amarulasolutions.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Wolfgang Grandegger <wg@aries-embedded.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
65 lines
1.4 KiB
Plaintext
65 lines
1.4 KiB
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_SOCFPGA=y
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CONFIG_SYS_TEXT_BASE=0x1000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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CONFIG_ENV_SIZE=0x1000
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CONFIG_ENV_OFFSET=0x200
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CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000
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CONFIG_DM_GPIO=y
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CONFIG_SPL_DM_SPI=y
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y
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CONFIG_IDENT_STRING="socfpga_agilex"
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CONFIG_SPL_FS_FAT=y
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CONFIG_SPL_TEXT_BASE=0xFFE00000
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CONFIG_BOOTDELAY=5
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="earlycon"
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CONFIG_SPL_CACHE=y
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CONFIG_SPL_SPI_LOAD=y
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CONFIG_HUSH_PARSER=y
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CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # "
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CONFIG_CMD_MEMTEST=y
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CONFIG_SYS_MEMTEST_START=0x00000000
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CONFIG_SYS_MEMTEST_END=0x3fe00000
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_OF_EMBED=y
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_SPL_DM_SEQ_ALIAS=y
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CONFIG_SPL_ALTERA_SDRAM=y
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CONFIG_DWAPB_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_DW=y
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CONFIG_DM_MMC=y
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CONFIG_MMC_DW=y
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CONFIG_SF_DEFAULT_MODE=0x2003
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_SPI_FLASH_STMICRO=y
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CONFIG_PHY_MICREL=y
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CONFIG_PHY_MICREL_KSZ90X1=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_MII=y
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CONFIG_DM_RESET=y
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CONFIG_SPI=y
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CONFIG_CADENCE_QSPI=y
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CONFIG_DESIGNWARE_SPI=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_DWC2=y
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CONFIG_USB_STORAGE=y
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# CONFIG_SPL_USE_TINY_PRINTF is not set
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