Sean Anderson c41045411b Revert "riscv: Clear pending interrupts before enabling IPIs" ... Clearing MIP.MSIP is not guaranteed to do anything by the spec. In addition, most existing RISC-V hardware does nothing when this bit is set. The following commits "riscv: Use a valid bit to ignore already-pending IPIs" and "riscv: Clear pending IPIs on initialization" should implement the original intent of the reverted commit in a more robust manner. This reverts commit 9472630337. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>		2020-09-30 08:54:52 +08:00
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cpu	Revert "riscv: Clear pending interrupts before enabling IPIs"	2020-09-30 08:54:52 +08:00
dts	riscv: Update SiFive device tree for new CLINT driver	2020-09-30 08:54:46 +08:00
include/asm	riscv: Rework Andes PLMT as a UCLASS_TIMER driver	2020-09-30 08:54:45 +08:00
lib	riscv: Rework Sifive CLINT as UCLASS_TIMER driver	2020-09-30 08:54:46 +08:00
config.mk	kconfig / kbuild: Re-sync with Linux 4.19	2020-04-10 11:18:32 -04:00
Kconfig	riscv: Rework Sifive CLINT as UCLASS_TIMER driver	2020-09-30 08:54:46 +08:00
Makefile	riscv: add Kconfig entries for the code model	2018-12-18 09:56:26 +08:00