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![Simon Glass](/assets/img/avatar_default.png)
Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
363 lines
9.3 KiB
C
363 lines
9.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012
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* Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <log.h>
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#include <asm-generic/io.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <reset.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <dm/device_compat.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/sizes.h>
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#include "cadence_qspi.h"
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#define CQSPI_STIG_READ 0
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#define CQSPI_STIG_WRITE 1
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#define CQSPI_READ 2
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#define CQSPI_WRITE 3
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static int cadence_spi_write_speed(struct udevice *bus, uint hz)
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{
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struct cadence_spi_plat *plat = dev_get_plat(bus);
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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cadence_qspi_apb_config_baudrate_div(priv->regbase,
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plat->ref_clk_hz, hz);
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/* Reconfigure delay timing if speed is changed. */
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cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
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plat->tshsl_ns, plat->tsd2d_ns,
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plat->tchsh_ns, plat->tslch_ns);
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return 0;
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}
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static int cadence_spi_read_id(void *reg_base, u8 len, u8 *idcode)
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{
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struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x9F, 1),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_DATA_IN(len, idcode, 1));
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return cadence_qspi_apb_command_read(reg_base, &op);
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}
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/* Calibration sequence to determine the read data capture delay register */
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static int spi_calibration(struct udevice *bus, uint hz)
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{
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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void *base = priv->regbase;
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unsigned int idcode = 0, temp = 0;
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int err = 0, i, range_lo = -1, range_hi = -1;
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/* start with slowest clock (1 MHz) */
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cadence_spi_write_speed(bus, 1000000);
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/* configure the read data capture delay register to 0 */
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cadence_qspi_apb_readdata_capture(base, 1, 0);
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/* Enable QSPI */
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cadence_qspi_apb_controller_enable(base);
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/* read the ID which will be our golden value */
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err = cadence_spi_read_id(base, 3, (u8 *)&idcode);
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if (err) {
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puts("SF: Calibration failed (read)\n");
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return err;
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}
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/* use back the intended clock and find low range */
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cadence_spi_write_speed(bus, hz);
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for (i = 0; i < CQSPI_READ_CAPTURE_MAX_DELAY; i++) {
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/* Disable QSPI */
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cadence_qspi_apb_controller_disable(base);
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/* reconfigure the read data capture delay register */
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cadence_qspi_apb_readdata_capture(base, 1, i);
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/* Enable back QSPI */
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cadence_qspi_apb_controller_enable(base);
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/* issue a RDID to get the ID value */
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err = cadence_spi_read_id(base, 3, (u8 *)&temp);
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if (err) {
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puts("SF: Calibration failed (read)\n");
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return err;
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}
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/* search for range lo */
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if (range_lo == -1 && temp == idcode) {
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range_lo = i;
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continue;
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}
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/* search for range hi */
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if (range_lo != -1 && temp != idcode) {
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range_hi = i - 1;
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break;
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}
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range_hi = i;
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}
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if (range_lo == -1) {
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puts("SF: Calibration failed (low range)\n");
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return err;
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}
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/* Disable QSPI for subsequent initialization */
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cadence_qspi_apb_controller_disable(base);
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/* configure the final value for read data capture delay register */
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cadence_qspi_apb_readdata_capture(base, 1, (range_hi + range_lo) / 2);
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debug("SF: Read data capture delay calibrated to %i (%i - %i)\n",
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(range_hi + range_lo) / 2, range_lo, range_hi);
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/* just to ensure we do once only when speed or chip select change */
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priv->qspi_calibrated_hz = hz;
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priv->qspi_calibrated_cs = spi_chip_select(bus);
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return 0;
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}
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static int cadence_spi_set_speed(struct udevice *bus, uint hz)
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{
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struct cadence_spi_plat *plat = dev_get_plat(bus);
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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int err;
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if (hz > plat->max_hz)
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hz = plat->max_hz;
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/* Disable QSPI */
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cadence_qspi_apb_controller_disable(priv->regbase);
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/*
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* Calibration required for different current SCLK speed, requested
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* SCLK speed or chip select
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*/
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if (priv->previous_hz != hz ||
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priv->qspi_calibrated_hz != hz ||
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priv->qspi_calibrated_cs != spi_chip_select(bus)) {
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err = spi_calibration(bus, hz);
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if (err)
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return err;
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/* prevent calibration run when same as previous request */
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priv->previous_hz = hz;
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}
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/* Enable QSPI */
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cadence_qspi_apb_controller_enable(priv->regbase);
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debug("%s: speed=%d\n", __func__, hz);
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return 0;
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}
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static int cadence_spi_probe(struct udevice *bus)
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{
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struct cadence_spi_plat *plat = dev_get_plat(bus);
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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struct clk clk;
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int ret;
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priv->regbase = plat->regbase;
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priv->ahbbase = plat->ahbbase;
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if (plat->ref_clk_hz == 0) {
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ret = clk_get_by_index(bus, 0, &clk);
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if (ret) {
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#ifdef CONFIG_CQSPI_REF_CLK
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plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
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#else
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return ret;
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#endif
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} else {
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plat->ref_clk_hz = clk_get_rate(&clk);
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clk_free(&clk);
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if (IS_ERR_VALUE(plat->ref_clk_hz))
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return plat->ref_clk_hz;
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}
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}
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ret = reset_get_bulk(bus, &priv->resets);
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if (ret)
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dev_warn(bus, "Can't get reset: %d\n", ret);
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else
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reset_deassert_bulk(&priv->resets);
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if (!priv->qspi_is_init) {
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cadence_qspi_apb_controller_init(plat);
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priv->qspi_is_init = 1;
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}
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return 0;
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}
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static int cadence_spi_remove(struct udevice *dev)
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{
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struct cadence_spi_priv *priv = dev_get_priv(dev);
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return reset_release_bulk(&priv->resets);
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}
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static int cadence_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct cadence_spi_plat *plat = dev_get_plat(bus);
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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/* Disable QSPI */
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cadence_qspi_apb_controller_disable(priv->regbase);
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/* Set SPI mode */
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cadence_qspi_apb_set_clk_mode(priv->regbase, mode);
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/* Enable Direct Access Controller */
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if (plat->use_dac_mode)
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cadence_qspi_apb_dac_mode_enable(priv->regbase);
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/* Enable QSPI */
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cadence_qspi_apb_controller_enable(priv->regbase);
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return 0;
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}
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static int cadence_spi_mem_exec_op(struct spi_slave *spi,
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const struct spi_mem_op *op)
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{
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struct udevice *bus = spi->dev->parent;
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struct cadence_spi_plat *plat = dev_get_plat(bus);
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struct cadence_spi_priv *priv = dev_get_priv(bus);
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void *base = priv->regbase;
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int err = 0;
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u32 mode;
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/* Set Chip select */
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cadence_qspi_apb_chipselect(base, spi_chip_select(spi->dev),
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plat->is_decoded_cs);
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if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) {
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if (!op->addr.nbytes)
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mode = CQSPI_STIG_READ;
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else
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mode = CQSPI_READ;
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} else {
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if (!op->addr.nbytes || !op->data.buf.out)
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mode = CQSPI_STIG_WRITE;
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else
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mode = CQSPI_WRITE;
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}
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switch (mode) {
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case CQSPI_STIG_READ:
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err = cadence_qspi_apb_command_read(base, op);
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break;
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case CQSPI_STIG_WRITE:
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err = cadence_qspi_apb_command_write(base, op);
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break;
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case CQSPI_READ:
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err = cadence_qspi_apb_read_setup(plat, op);
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if (!err)
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err = cadence_qspi_apb_read_execute(plat, op);
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break;
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case CQSPI_WRITE:
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err = cadence_qspi_apb_write_setup(plat, op);
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if (!err)
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err = cadence_qspi_apb_write_execute(plat, op);
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break;
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default:
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err = -1;
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break;
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}
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return err;
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}
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static int cadence_spi_of_to_plat(struct udevice *bus)
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{
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struct cadence_spi_plat *plat = dev_get_plat(bus);
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ofnode subnode;
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plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
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plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1,
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&plat->ahbsize);
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plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs");
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plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128);
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plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
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plat->trigger_address = dev_read_u32_default(bus,
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"cdns,trigger-address",
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0);
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/* Use DAC mode only when MMIO window is at least 8M wide */
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if (plat->ahbsize >= SZ_8M)
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plat->use_dac_mode = true;
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/* All other paramters are embedded in the child node */
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subnode = dev_read_first_subnode(bus);
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if (!ofnode_valid(subnode)) {
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printf("Error: subnode with SPI flash config missing!\n");
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return -ENODEV;
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}
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/* Use 500 KHz as a suitable default */
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plat->max_hz = ofnode_read_u32_default(subnode, "spi-max-frequency",
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500000);
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/* Read other parameters from DT */
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plat->page_size = ofnode_read_u32_default(subnode, "page-size", 256);
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plat->block_size = ofnode_read_u32_default(subnode, "block-size", 16);
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plat->tshsl_ns = ofnode_read_u32_default(subnode, "cdns,tshsl-ns",
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200);
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plat->tsd2d_ns = ofnode_read_u32_default(subnode, "cdns,tsd2d-ns",
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255);
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plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
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plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
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debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
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__func__, plat->regbase, plat->ahbbase, plat->max_hz,
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plat->page_size);
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return 0;
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}
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static const struct spi_controller_mem_ops cadence_spi_mem_ops = {
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.exec_op = cadence_spi_mem_exec_op,
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};
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static const struct dm_spi_ops cadence_spi_ops = {
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.set_speed = cadence_spi_set_speed,
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.set_mode = cadence_spi_set_mode,
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.mem_ops = &cadence_spi_mem_ops,
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/*
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* cs_info is not needed, since we require all chip selects to be
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* in the device tree explicitly
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*/
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};
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static const struct udevice_id cadence_spi_ids[] = {
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{ .compatible = "cdns,qspi-nor" },
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{ .compatible = "ti,am654-ospi" },
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{ }
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};
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U_BOOT_DRIVER(cadence_spi) = {
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.name = "cadence_spi",
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.id = UCLASS_SPI,
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.of_match = cadence_spi_ids,
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.ops = &cadence_spi_ops,
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.of_to_plat = cadence_spi_of_to_plat,
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.plat_auto = sizeof(struct cadence_spi_plat),
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.priv_auto = sizeof(struct cadence_spi_priv),
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.probe = cadence_spi_probe,
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.remove = cadence_spi_remove,
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.flags = DM_FLAG_OS_PREPARE,
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};
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