mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
c34a927566
Add CAxxxx Ethernet support for the Cortina Access Presidio Engineering Board Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Tom Rini <trini@konsulko.com>
144 lines
3.0 KiB
Plaintext
144 lines
3.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020, Cortina Access Inc.
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*/
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/dts-v1/;
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/ {
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#address-cells = <2>;
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#size-cells = <1>;
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mmc0: mmc@f4400000 {
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compatible = "cortina,ca-mmc";
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reg = <0x0 0xf4400000 0x1000>;
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bus-width = <4>;
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sd_dll_ctrl = <0xf43200e8>;
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io_drv_ctrl = <0xf432004c>;
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};
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gpio0: gpio-controller@0xf4329280 {
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compatible = "cortina,ca-gpio";
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reg = <0x0 0xf4329280 0x24>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "okay";
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};
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gpio1: gpio-controller@0xf43292a4 {
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compatible = "cortina,ca-gpio";
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reg = <0x0 0xf43292a4 0x24>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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watchdog: watchdog@0xf432901c {
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compatible = "cortina,ca-wdt";
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reg = <0x0 0xf432901c 0x34>,
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<0x0 0xf4320020 0x04>;
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status = "okay";
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};
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uart0: serial@0xf4329148 {
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u-boot,dm-pre-reloc;
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compatible = "cortina,ca-uart";
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reg = <0x0 0xf4329148 0x30>;
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status = "okay";
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};
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i2c: i2c@f4329120 {
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compatible = "cortina,ca-i2c";
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reg = <0x0 0xf4329120 0x28>;
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clock-frequency = <400000>;
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};
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nand: nand-controller@f4324000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "cortina,ca-nand";
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reg = <0 0xf4324000 0x3b0>, /* NAND controller */
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<0 0xf7001000 0xb4>, /* DMA_GLOBAL */
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<0 0xf7001a00 0x80>; /* DMA channel0 for FLASH */
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status = "okay";
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nand-ecc-mode = "hw";
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nand-ecc-strength = <16>;
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nand-ecc-step-size = <1024>; /* Must be 1024 */
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nand_flash_base_addr = <0xe0000000>;
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};
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sflash: sflash-controller@f4324000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "cortina,ca-sflash";
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reg = <0x0 0xf4324000 0x50>;
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reg-names = "sflash-regs";
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flash@0 {
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compatible = "jedec,spi-nor";
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spi-rx-bus-width = <1>;
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spi-max-frequency = <108000000>;
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};
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};
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leds: led-controller@f43200f0 {
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compatible = "cortina,ca-leds";
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reg = <0x0 0xf43200f0 0x40>;
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cortina,blink-rate1 = <256>;
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cortina,blink-rate2 = <512>;
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led@0 {
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pin = <0>;
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active-low;
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blink-sel =<0>;
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port = <0>;
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off-event = <0>;
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label = "led0";
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};
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led@1 {
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pin = <1>;
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active-low;
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blink-sel =<1>;
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label = "led1";
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};
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led@2 {
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pin = <2>;
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active-low;
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label = "led2";
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};
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};
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eth: ethnet@0xf4300000 {
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compatible = "eth_cortina";
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reg = <0x0 0xf4320000 0x34>,
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<0x0 0xf43290d8 0x04>,
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<0x0 0xf4304000 0x04>;
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/* port0: phy address 1 - GMAC0: port 0
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* port1: phy address 2 - GMAC1: port 1
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* port2: phy address 3 - GMAC2: port 2
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* port3: phy address 4 - GMAC3: port 3
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* port4: phy address 5 - RGMII: port 4
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*/
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valid-port-map = <0x1f>;
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valid-port-num = <5>;
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valid-ports = <0x1 0x0>,
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<0x2 0x1>,
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<0x3 0x2>,
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<0x4 0x3>,
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<0x5 0x4>;
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def-active-port = <0x3>;
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inter-gphy-num = <6>;
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inter-gphy-val = <0xf43380fc 0xbcd>,
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<0xf43380dc 0xeeee>,
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<0xf43380d8 0xeeee>,
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<0xf43380fc 0xbce>,
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<0xf43380c0 0x7777>,
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<0xf43380c4 0x7777>;
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init-rgmii = <1>;
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ni-xram-base = <0xF4500000>;
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};
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};
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