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board: presidio-asic: Add CAxxxx Ethernet support 

Add CAxxxx Ethernet support for the Cortina Access
Presidio Engineering Board

Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Tom Rini <trini@konsulko.com>
This commit is contained in:
Alex Nemirovsky 2021-01-14 13:34:13 -08:00 committed by Tom Rini
parent a70d7b0192
commit c34a927566
3 changed files with 48 additions and 2 deletions
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31
arch/arm/dts/ca-presidio-engboard.dts
View File

@ -109,4 +109,35 @@
};
};
eth: ethnet@0xf4300000 {
compatible = "eth_cortina";
reg = <0x0 0xf4320000 0x34>,
<0x0 0xf43290d8 0x04>,
<0x0 0xf4304000 0x04>;
/* port0: phy address 1 - GMAC0: port 0
* port1: phy address 2 - GMAC1: port 1
* port2: phy address 3 - GMAC2: port 2
* port3: phy address 4 - GMAC3: port 3
* port4: phy address 5 - RGMII: port 4
*/
valid-port-map = <0x1f>;
valid-port-num = <5>;
valid-ports = <0x1 0x0>,
<0x2 0x1>,
<0x3 0x2>,
<0x4 0x3>,
<0x5 0x4>;
def-active-port = <0x3>;
inter-gphy-num = <6>;
inter-gphy-val = <0xf43380fc 0xbcd>,
<0xf43380dc 0xeeee>,
<0xf43380d8 0xeeee>,
<0xf43380fc 0xbce>,
<0xf43380c0 0x7777>,
<0xf43380c4 0x7777>;
init-rgmii = <1>;
ni-xram-base = <0xF4500000>;
};
};

4
configs/cortina_presidio-asic-emmc_defconfig
View File

@ -22,7 +22,6 @@ CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIVE=y
# CONFIG_NET is not set
CONFIG_DM=y
CONFIG_CORTINA_GPIO=y
CONFIG_DM_I2C=y
@ -30,6 +29,9 @@ CONFIG_SYS_I2C_CA=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_CORTINA=y
CONFIG_PHYLIB=y
CONFIG_DM_ETH=y
CONFIG_CORTINA_NI_ENET=y
CONFIG_DM_SERIAL=y
CONFIG_CORTINA_UART=y
CONFIG_WDT=y

15
include/configs/presidio_asic.h
View File

@ -2,7 +2,7 @@
/*
* Copyright (C) 2020 Cortina Access Inc.
*
* Configuration for Cortina-Access Presidio board.
* Configuration for Cortina-Access Presidio board
*/
#ifndef __PRESIDIO_ASIC_H
@ -63,6 +63,19 @@
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define KSEG1_ATU_XLAT(x) (x)
/* HW REG ADDR */
#define NI_READ_POLL_COUNT 1000
#define CA_NI_MDIO_REG_BASE 0xF4338
#define NI_HV_GLB_MAC_ADDR_CFG0_OFFSET 0x010
#define NI_HV_GLB_MAC_ADDR_CFG1_OFFSET 0x014
#define NI_HV_PT_BASE 0x400
#define NI_HV_XRAM_BASE 0x820
#define GLOBAL_BLOCK_RESET_OFFSET 0x04
#define GLOBAL_GLOBAL_CONFIG_OFFSET 0x20
#define GLOBAL_IO_DRIVE_CONTROL_OFFSET 0x4c
/* max command args */
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0"