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https://github.com/brain-hackers/u-boot-brain
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90526e9fba
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by: Simon Glass <sjg@chromium.org>
173 lines
2.9 KiB
C
173 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <asm/cache.h>
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#include <dm/uclass-internal.h>
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#include <cache.h>
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#include <asm/csr.h>
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#ifdef CONFIG_RISCV_NDS_CACHE
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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/* mcctlcommand */
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#define CCTL_REG_MCCTLCOMMAND_NUM 0x7cc
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/* D-cache operation */
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#define CCTL_L1D_WBINVAL_ALL 6
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#endif
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#endif
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#ifdef CONFIG_V5L2_CACHE
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static void _cache_enable(void)
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{
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struct udevice *dev = NULL;
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uclass_find_first_device(UCLASS_CACHE, &dev);
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if (dev)
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cache_enable(dev);
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}
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static void _cache_disable(void)
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{
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struct udevice *dev = NULL;
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uclass_find_first_device(UCLASS_CACHE, &dev);
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if (dev)
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cache_disable(dev);
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}
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#endif
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void flush_dcache_all(void)
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{
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#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
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#ifdef CONFIG_RISCV_NDS_CACHE
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
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#endif
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#endif
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#endif
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}
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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flush_dcache_all();
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}
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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flush_dcache_all();
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}
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void icache_enable(void)
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{
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#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
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#ifdef CONFIG_RISCV_NDS_CACHE
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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asm volatile (
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"csrr t1, mcache_ctl\n\t"
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"ori t0, t1, 0x1\n\t"
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"csrw mcache_ctl, t0\n\t"
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);
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#endif
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#endif
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#endif
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}
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void icache_disable(void)
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{
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#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
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#ifdef CONFIG_RISCV_NDS_CACHE
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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asm volatile (
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"fence.i\n\t"
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"csrr t1, mcache_ctl\n\t"
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"andi t0, t1, ~0x1\n\t"
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"csrw mcache_ctl, t0\n\t"
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);
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#endif
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#endif
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#endif
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}
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void dcache_enable(void)
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{
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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#ifdef CONFIG_RISCV_NDS_CACHE
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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asm volatile (
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"csrr t1, mcache_ctl\n\t"
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"ori t0, t1, 0x2\n\t"
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"csrw mcache_ctl, t0\n\t"
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);
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#endif
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#ifdef CONFIG_V5L2_CACHE
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_cache_enable();
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#endif
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#endif
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#endif
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}
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void dcache_disable(void)
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{
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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#ifdef CONFIG_RISCV_NDS_CACHE
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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csr_write(CCTL_REG_MCCTLCOMMAND_NUM, CCTL_L1D_WBINVAL_ALL);
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asm volatile (
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"csrr t1, mcache_ctl\n\t"
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"andi t0, t1, ~0x2\n\t"
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"csrw mcache_ctl, t0\n\t"
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);
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#endif
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#ifdef CONFIG_V5L2_CACHE
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_cache_disable();
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#endif
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#endif
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#endif
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}
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int icache_status(void)
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{
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int ret = 0;
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#ifdef CONFIG_RISCV_NDS_CACHE
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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asm volatile (
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"csrr t1, mcache_ctl\n\t"
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"andi %0, t1, 0x01\n\t"
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: "=r" (ret)
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:
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: "memory"
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);
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#endif
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#endif
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return ret;
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}
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int dcache_status(void)
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{
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int ret = 0;
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#ifdef CONFIG_RISCV_NDS_CACHE
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#if CONFIG_IS_ENABLED(RISCV_MMODE)
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asm volatile (
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"csrr t1, mcache_ctl\n\t"
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"andi %0, t1, 0x02\n\t"
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: "=r" (ret)
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:
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: "memory"
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);
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#endif
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#endif
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return ret;
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}
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