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https://github.com/brain-hackers/u-boot-brain
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7dbebebb79
This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
25 lines
667 B
Plaintext
25 lines
667 B
Plaintext
config RISCV_NDS
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bool
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select ARCH_EARLY_INIT_R
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imply CPU
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imply CPU_RISCV
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imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
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imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
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imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
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imply SPL_CPU_SUPPORT
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imply SPL_OPENSBI
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imply SPL_LOAD_FIT
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help
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Run U-Boot on AndeStar V5 platforms and use some specific features
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which are provided by Andes Technology AndeStar V5 families.
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if RISCV_NDS
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config RISCV_NDS_CACHE
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bool "AndeStar V5 families specific cache support"
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depends on RISCV_MMODE || SPL_RISCV_MMODE
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help
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Provide Andes Technology AndeStar V5 families specific cache support.
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endif
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