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https://github.com/brain-hackers/u-boot-brain
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000f4e7686
As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
184 lines
4.0 KiB
C
184 lines
4.0 KiB
C
/*
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* Copyright 2014-2015 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fsl_ifc.h>
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#include <asm/arch/soc.h>
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#include <asm/io.h>
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#include <asm/global_data.h>
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#include <asm/arch-fsl-layerscape/config.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
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/*
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* This erratum requires setting a value to eddrtqcr1 to
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* optimal the DDR performance.
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*/
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static void erratum_a008336(void)
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{
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u32 *eddrtqcr1;
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
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#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
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eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
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out_le32(eddrtqcr1, 0x63b30002);
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#endif
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#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
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eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
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out_le32(eddrtqcr1, 0x63b30002);
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#endif
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#endif
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}
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/*
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* This erratum requires a register write before being Memory
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* controller 3 being enabled.
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*/
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static void erratum_a008514(void)
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{
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u32 *eddrtqcr1;
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
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#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
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eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
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out_le32(eddrtqcr1, 0x63b20002);
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#endif
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#endif
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}
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
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#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
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static unsigned long get_internval_val_mhz(void)
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{
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char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
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/*
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* interval is the number of platform cycles(MHz) between
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* wake up events generated by EPU.
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*/
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ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
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if (interval)
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interval_mhz = simple_strtoul(interval, NULL, 10);
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return interval_mhz;
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}
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void erratum_a009635(void)
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{
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u32 val;
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unsigned long interval_mhz = get_internval_val_mhz();
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if (!interval_mhz)
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return;
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val = in_le32(DCSR_CGACRE5);
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writel(val | 0x00000200, DCSR_CGACRE5);
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val = in_le32(EPU_EPCMPR5);
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writel(interval_mhz, EPU_EPCMPR5);
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val = in_le32(EPU_EPCCR5);
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writel(val | 0x82820000, EPU_EPCCR5);
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val = in_le32(EPU_EPSMCR5);
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writel(val | 0x002f0000, EPU_EPSMCR5);
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val = in_le32(EPU_EPECR5);
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writel(val | 0x20000000, EPU_EPECR5);
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val = in_le32(EPU_EPGCR);
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writel(val | 0x80000000, EPU_EPGCR);
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}
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#endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
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static void erratum_a008751(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008751
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u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
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writel(0x27672b2a, scfg + SCFG_USB3PRM1CR / 4);
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#endif
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}
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static void erratum_rcw_src(void)
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{
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#if defined(CONFIG_SPL)
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u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
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u32 __iomem *dcfg_dcsr = (u32 __iomem *)DCFG_DCSR_BASE;
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u32 val;
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val = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
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val &= ~DCFG_PORSR1_RCW_SRC;
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val |= DCFG_PORSR1_RCW_SRC_NOR;
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out_le32(dcfg_dcsr + DCFG_DCSR_PORCR1 / 4, val);
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#endif
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}
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#define I2C_DEBUG_REG 0x6
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#define I2C_GLITCH_EN 0x8
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/*
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* This erratum requires setting glitch_en bit to enable
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* digital glitch filter to improve clock stability.
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*/
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static void erratum_a009203(void)
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{
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u8 __iomem *ptr;
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#ifdef CONFIG_SYS_I2C
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#ifdef I2C1_BASE_ADDR
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ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
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writeb(I2C_GLITCH_EN, ptr);
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#endif
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#ifdef I2C2_BASE_ADDR
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ptr = (u8 __iomem *)(I2C2_BASE_ADDR + I2C_DEBUG_REG);
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writeb(I2C_GLITCH_EN, ptr);
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#endif
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#ifdef I2C3_BASE_ADDR
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ptr = (u8 __iomem *)(I2C3_BASE_ADDR + I2C_DEBUG_REG);
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writeb(I2C_GLITCH_EN, ptr);
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#endif
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#ifdef I2C4_BASE_ADDR
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ptr = (u8 __iomem *)(I2C4_BASE_ADDR + I2C_DEBUG_REG);
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writeb(I2C_GLITCH_EN, ptr);
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#endif
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#endif
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}
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void fsl_lsch3_early_init_f(void)
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{
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erratum_a008751();
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erratum_rcw_src();
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init_early_memctl_regs(); /* tighten IFC timing */
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erratum_a009203();
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erratum_a008514();
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erratum_a008336();
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}
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#elif defined(CONFIG_LS1043A)
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void fsl_lsch2_early_init_f(void)
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
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#ifdef CONFIG_FSL_IFC
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init_early_memctl_regs(); /* tighten IFC timing */
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#endif
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/*
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* Enable snoop requests and DVM message requests for
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* Slave insterface S4 (A53 core cluster)
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*/
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out_le32(&cci->slave[4].snoop_ctrl,
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CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
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}
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#endif
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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return 0;
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}
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#endif
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