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https://github.com/brain-hackers/u-boot-brain
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![Alison Wang](/assets/img/avatar_default.png)
As QSPI/DSPI and IFC are pin multiplexed, IFC is disabled in SD boot for QSPI. This patch will add fdt support for this rule. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
187 lines
5.0 KiB
C
187 lines
5.0 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/arch/clock.h>
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#include <linux/ctype.h>
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#ifdef CONFIG_FSL_ESDHC
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#include <fsl_esdhc.h>
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#endif
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#include <tsec.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <fsl_sec.h>
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DECLARE_GLOBAL_DATA_PTR;
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void ft_fixup_enet_phy_connect_type(void *fdt)
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{
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struct eth_device *dev;
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struct tsec_private *priv;
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const char *enet_path, *phy_path;
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char enet[16];
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char phy[16];
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int phy_node;
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int i = 0;
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uint32_t ph;
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while ((dev = eth_get_dev_by_index(i++)) != NULL) {
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if (strstr(dev->name, "eTSEC1")) {
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strcpy(enet, "ethernet0");
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strcpy(phy, "enet0_rgmii_phy");
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} else if (strstr(dev->name, "eTSEC2")) {
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strcpy(enet, "ethernet1");
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strcpy(phy, "enet1_rgmii_phy");
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} else if (strstr(dev->name, "eTSEC3")) {
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strcpy(enet, "ethernet2");
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strcpy(phy, "enet2_rgmii_phy");
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} else {
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continue;
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}
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priv = dev->priv;
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if (priv->flags & TSEC_SGMII)
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continue;
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enet_path = fdt_get_alias(fdt, enet);
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if (!enet_path)
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continue;
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phy_path = fdt_get_alias(fdt, phy);
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if (!phy_path)
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continue;
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phy_node = fdt_path_offset(fdt, phy_path);
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if (phy_node < 0)
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continue;
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ph = fdt_create_phandle(fdt, phy_node);
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if (ph)
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do_fixup_by_path_u32(fdt, enet_path,
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"phy-handle", ph, 1);
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do_fixup_by_path(fdt, enet_path, "phy-connection-type",
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phy_string_for_interface(
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PHY_INTERFACE_MODE_RGMII_ID),
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sizeof(phy_string_for_interface(
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PHY_INTERFACE_MODE_RGMII_ID)),
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1);
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}
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}
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void ft_cpu_setup(void *blob, bd_t *bd)
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{
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int off;
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int val;
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const char *sysclk_path;
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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unsigned int svr;
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svr = in_be32(&gur->svr);
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unsigned long busclk = get_bus_freq(0);
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/* delete crypto node if not on an E-processor */
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if (!IS_E_PROCESSOR(svr))
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fdt_fixup_crypto_node(blob, 0);
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#if CONFIG_SYS_FSL_SEC_COMPAT >= 4
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else {
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ccsr_sec_t __iomem *sec;
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sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
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fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
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}
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#endif
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fdt_fixup_ethernet(blob);
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off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
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while (off != -FDT_ERR_NOTFOUND) {
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val = gd->cpu_clk;
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fdt_setprop(blob, off, "clock-frequency", &val, 4);
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off = fdt_node_offset_by_prop_value(blob, off,
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"device_type", "cpu", 4);
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}
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do_fixup_by_prop_u32(blob, "device_type", "soc",
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4, "bus-frequency", busclk, 1);
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ft_fixup_enet_phy_connect_type(blob);
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#ifdef CONFIG_SYS_NS16550
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do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
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"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
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#endif
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sysclk_path = fdt_get_alias(blob, "sysclk");
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if (sysclk_path)
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do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
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CONFIG_SYS_CLK_FREQ, 1);
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do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
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"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
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#if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
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#define UBOOT_HEAD_LEN 0x1000
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/*
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* Reserved memory in SD boot deep sleep case.
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* Second stage uboot binary and malloc space should be reserved.
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* If the memory they occupied has not been reserved, then this
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* space would be used by kernel and overwritten in uboot when
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* deep sleep resume, which cause deep sleep failed.
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* Since second uboot binary has a head, that space need to be
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* reserved either(assuming its size is less than 0x1000).
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*/
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off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
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CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
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UBOOT_HEAD_LEN);
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if (off < 0)
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printf("Failed to reserve memory for SD boot deep sleep: %s\n",
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fdt_strerror(off));
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#endif
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#if defined(CONFIG_FSL_ESDHC)
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fdt_fixup_esdhc(blob, bd);
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#endif
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/*
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* platform bus clock = system bus clock/2
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* Here busclk = system bus clock
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* We are using the platform bus clock as 1588 Timer reference
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* clock source select
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*/
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do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
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"timer-frequency", busclk / 2, 1);
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/*
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* clock-freq should change to clock-frequency and
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* flexcan-v1.0 should change to p1010-flexcan respectively
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* in the future.
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*/
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do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
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"clock_freq", busclk / 2, 1);
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do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
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"clock-frequency", busclk / 2, 1);
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do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
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"clock-frequency", busclk / 2, 1);
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
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CONFIG_SYS_IFC_ADDR);
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fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
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#else
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off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
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QSPI0_BASE_ADDR);
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fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
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off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
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DSPI1_BASE_ADDR);
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fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
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#endif
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}
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