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https://github.com/brain-hackers/u-boot-brain
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a27520904f
Add a few more CPU functions that are common on Intel CPUs. Also add
attribution for the code source.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add missing MSR_IA32_MISC_ENABLE write back in cpu_set_eist();
fix 2 typos in cpu_get_burst_mode_state() comments]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
132 lines
3.2 KiB
C
132 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Common code for Intel CPUs
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*
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* Copyright (c) 2016 Google, Inc
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*/
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#ifndef __ASM_CPU_COMMON_H
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#define __ASM_CPU_COMMON_H
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/* Standard Intel bus clock is fixed at 100MHz */
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enum {
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INTEL_BCLK_MHZ = 100
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};
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struct cpu_info;
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/**
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* cpu_common_init() - Set up common CPU init
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*
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* This reports BIST failure, enables the LAPIC, updates microcode, enables
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* the upper 128-bytes of CROM RAM, probes the northbridge, PCH, LPC and SATA.
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*
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* @return 0 if OK, -ve on error
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*/
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int cpu_common_init(void);
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/**
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* cpu_set_flex_ratio_to_tdp_nominal() - Set up the maximum non-turbo rate
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*
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* If a change is needed, this function will do a soft reset so it takes
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* effect.
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*
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* Some details are available here:
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* http://forum.hwbot.org/showthread.php?t=76092
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*
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* @return 0 if OK, -ve on error
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*/
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int cpu_set_flex_ratio_to_tdp_nominal(void);
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/**
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* cpu_intel_get_info() - Obtain CPU info for Intel CPUs
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*
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* Most Intel CPUs use the same MSR to obtain the clock speed, and use the same
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* features. This function fills in these values, given the value of the base
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* clock in MHz (typically this should be set to 100).
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*
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* @info: cpu_info struct to fill in
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* @bclk_mz: the base clock in MHz
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*
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* @return 0 always
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*/
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int cpu_intel_get_info(struct cpu_info *info, int bclk_mz);
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/**
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* cpu_configure_thermal_target() - Set the thermal target for a CPU
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*
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* This looks up the tcc-offset property and uses it to set the
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* MSR_TEMPERATURE_TARGET value.
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*
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* @dev: CPU device
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* @return 0 if OK, -ENOENT if no target is given in device tree
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*/
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int cpu_configure_thermal_target(struct udevice *dev);
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/**
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* cpu_set_perf_control() - Set the nominal CPU clock speed
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*
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* This sets the clock speed as a multiplier of BCLK
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*
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* @clk_ratio: Ratio to use
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*/
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void cpu_set_perf_control(uint clk_ratio);
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/**
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* cpu_config_tdp_levels() - Check for configurable TDP option
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*
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* @return true if the CPU has configurable TDP (Thermal-design power)
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*/
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bool cpu_config_tdp_levels(void);
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/** enum burst_mode_t - Burst-mode states */
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enum burst_mode_t {
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BURST_MODE_UNKNOWN,
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BURST_MODE_UNAVAILABLE,
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BURST_MODE_DISABLED,
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BURST_MODE_ENABLED
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};
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/*
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* cpu_get_burst_mode_state() - Get the Burst/Turbo Mode State
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*
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* This reads MSR IA32_MISC_ENABLE 0x1A0
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* Bit 38 - TURBO_MODE_DISABLE Bit to get state ENABLED / DISABLED.
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* Also checks cpuid 0x6 to see whether burst mode is supported.
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*
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* @return current burst mode status
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*/
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enum burst_mode_t cpu_get_burst_mode_state(void);
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/**
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* cpu_set_burst_mode() - Set CPU burst mode
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*
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* @burst_mode: true to enable burst mode, false to disable
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*/
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void cpu_set_burst_mode(bool burst_mode);
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/**
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* cpu_set_eist() - Enable Enhanced Intel Speed Step Technology
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*
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* @eist_status: true to enable EIST, false to disable
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*/
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void cpu_set_eist(bool eist_status);
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/**
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* cpu_set_p_state_to_turbo_ratio() - Set turbo ratio
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*
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* TURBO_RATIO_LIMIT MSR (0x1AD) Bits 31:0 indicates the
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* factory configured values for of 1-core, 2-core, 3-core
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* and 4-core turbo ratio limits for all processors.
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*
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* 7:0 - MAX_TURBO_1_CORE
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* 15:8 - MAX_TURBO_2_CORES
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* 23:16 - MAX_TURBO_3_CORES
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* 31:24 - MAX_TURBO_4_CORES
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*
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* Set PERF_CTL MSR (0x199) P_Req with that value.
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*/
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void cpu_set_p_state_to_turbo_ratio(void);
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#endif
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