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x86: Add new common CPU functions for turbo/burst mode

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Add a few more CPU functions that are common on Intel CPUs. Also add
attribution for the code source.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add missing MSR_IA32_MISC_ENABLE write back in cpu_set_eist();
        fix 2 typos in cpu_get_burst_mode_state() comments]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2019-09-25 08:56:40 -06:00 committed by Bin Meng
parent f6d00da459
commit a27520904f
2 changed files with 110 additions and 0 deletions
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61
arch/x86/cpu/intel_common/cpu.c
View File

@ -1,12 +1,17 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2014 Google Inc.
* Copyright (c) 2016 Google, Inc
* Copyright (C) 2015-2018 Intel Corporation.
* Copyright (C) 2018 Siemens AG
* Some code taken from coreboot cpulib.c
*/
#include <common.h>
#include <cpu.h>
#include <dm.h>
#include <errno.h>
#include <asm/cpu.h>
#include <asm/cpu_common.h>
#include <asm/intel_regs.h>
#include <asm/lapic.h>
@ -165,3 +170,59 @@ bool cpu_config_tdp_levels(void)
return ((platform_info.hi >> 1) & 3) != 0;
}
void cpu_set_p_state_to_turbo_ratio(void)
{
msr_t msr;
msr = msr_read(MSR_TURBO_RATIO_LIMIT);
cpu_set_perf_control(msr.lo);
}
enum burst_mode_t cpu_get_burst_mode_state(void)
{
enum burst_mode_t state;
int burst_en, burst_cap;
msr_t msr;
uint eax;
eax = cpuid_eax(0x6);
burst_cap = eax & 0x2;
msr = msr_read(MSR_IA32_MISC_ENABLE);
burst_en = !(msr.hi & BURST_MODE_DISABLE);
if (!burst_cap && burst_en)
state = BURST_MODE_UNAVAILABLE;
else if (burst_cap && !burst_en)
state = BURST_MODE_DISABLED;
else if (burst_cap && burst_en)
state = BURST_MODE_ENABLED;
else
state = BURST_MODE_UNKNOWN;
return state;
}
void cpu_set_burst_mode(bool burst_mode)
{
msr_t msr;
msr = msr_read(MSR_IA32_MISC_ENABLE);
if (burst_mode)
msr.hi &= ~BURST_MODE_DISABLE;
else
msr.hi |= BURST_MODE_DISABLE;
msr_write(MSR_IA32_MISC_ENABLE, msr);
}
void cpu_set_eist(bool eist_status)
{
msr_t msr;
msr = msr_read(MSR_IA32_MISC_ENABLE);
if (eist_status)
msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP;
else
msr.lo &= ~MISC_ENABLE_ENHANCED_SPEEDSTEP;
msr_write(MSR_IA32_MISC_ENABLE, msr);
}

49
arch/x86/include/asm/cpu_common.h
View File

@ -79,4 +79,53 @@ void cpu_set_perf_control(uint clk_ratio);
*/
bool cpu_config_tdp_levels(void);
/** enum burst_mode_t - Burst-mode states */
enum burst_mode_t {
BURST_MODE_UNKNOWN,
BURST_MODE_UNAVAILABLE,
BURST_MODE_DISABLED,
BURST_MODE_ENABLED
};
/*
* cpu_get_burst_mode_state() - Get the Burst/Turbo Mode State
*
* This reads MSR IA32_MISC_ENABLE 0x1A0
* Bit 38 - TURBO_MODE_DISABLE Bit to get state ENABLED / DISABLED.
* Also checks cpuid 0x6 to see whether burst mode is supported.
*
* @return current burst mode status
*/
enum burst_mode_t cpu_get_burst_mode_state(void);
/**
* cpu_set_burst_mode() - Set CPU burst mode
*
* @burst_mode: true to enable burst mode, false to disable
*/
void cpu_set_burst_mode(bool burst_mode);
/**
* cpu_set_eist() - Enable Enhanced Intel Speed Step Technology
*
* @eist_status: true to enable EIST, false to disable
*/
void cpu_set_eist(bool eist_status);
/**
* cpu_set_p_state_to_turbo_ratio() - Set turbo ratio
*
* TURBO_RATIO_LIMIT MSR (0x1AD) Bits 31:0 indicates the
* factory configured values for of 1-core, 2-core, 3-core
* and 4-core turbo ratio limits for all processors.
*
* 7:0 - MAX_TURBO_1_CORE
* 15:8 - MAX_TURBO_2_CORES
* 23:16 - MAX_TURBO_3_CORES
* 31:24 - MAX_TURBO_4_CORES
*
* Set PERF_CTL MSR (0x199) P_Req with that value.
*/
void cpu_set_p_state_to_turbo_ratio(void);
#endif