Tom Warren b77c3547e8 Tegra114: fdt: Update DT files with I2C info for T114/Dalmore ... T114, like T30, does not have a separate/different DVC (power I2C) controller like T20 - all 5 I2C controllers are identical, but I2C5 is used to designate the controller intended for power control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>		2013-03-14 11:06:41 -07:00
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cpu	Tegra114: I2C: Take DVFS out of reset to allow I2C5 (PWR_I2C) to work	2013-03-14 11:06:41 -07:00
dts	Tegra114: fdt: Update DT files with I2C info for T114/Dalmore	2013-03-14 11:06:41 -07:00
imx-common	Merge branch 'master' of git://git.denx.de/u-boot-arm	2013-02-12 10:18:31 -05:00
include/asm	Tegra: I2C: Add T114 clock support to tegra_i2c driver	2013-03-14 11:06:41 -07:00
lib	arm: make __bss_start and __bss_end__ compiler-generated	2013-03-12 23:28:32 +01:00
config.mk	arm: work around assembler bug	2012-10-04 14:19:04 +02:00