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b777789ebd
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <van.freenix@gmail.com> Acked-by: Stefano Babic <sbabic@denx.de> |
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| .. | ||
| arm11 | ||
| arm720t | ||
| arm920t | ||
| arm926ejs | ||
| arm946es | ||
| arm1136 | ||
| arm1176 | ||
| armv7 | ||
| armv7m | ||
| armv8 | ||
| pxa | ||
| sa1100 | ||
| Makefile | ||
| u-boot-spl.lds | ||
| u-boot.lds | ||