mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 20:56:16 +09:00
4fa4267d82
Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
6 lines
162 B
Makefile
6 lines
162 B
Makefile
|
|
obj-$(CONFIG_CACHE) += cache-uclass.o
|
|
obj-$(CONFIG_SANDBOX) += sandbox_cache.o
|
|
obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
|
|
obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
|