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https://github.com/brain-hackers/u-boot-brain
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dm: cache: add v5l2 cache controller driver
Add a v5l2 cache controller driver that is usually found on Andes RISC-V ae350 platform. It will parse the cache settings from the dtb. In this version tag and data ram control timing can be adjusted by the requirement from the dtb. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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9
drivers/cache/Kconfig
vendored
9
drivers/cache/Kconfig
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@ -22,4 +22,13 @@ config L2X0_CACHE
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ARMv7(32-bit) devices. The driver configures the cache settings
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found in the device tree.
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config V5L2_CACHE
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bool "Andes V5L2 cache driver"
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select CACHE
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depends on RISCV_NDS_CACHE
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help
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Support Andes V5L2 cache controller in AE350 platform.
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It will configure tag and data ram timing control from the
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device tree and enable L2 cache.
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endmenu
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1
drivers/cache/Makefile
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1
drivers/cache/Makefile
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@ -2,3 +2,4 @@
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obj-$(CONFIG_CACHE) += cache-uclass.o
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obj-$(CONFIG_SANDBOX) += sandbox_cache.o
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obj-$(CONFIG_L2X0_CACHE) += cache-l2x0.o
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obj-$(CONFIG_V5L2_CACHE) += cache-v5l2.o
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186
drivers/cache/cache-v5l2.c
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Normal file
186
drivers/cache/cache-v5l2.c
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Normal file
@ -0,0 +1,186 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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#include <common.h>
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#include <command.h>
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#include <cache.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <dm/ofnode.h>
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struct l2cache {
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volatile u64 configure;
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volatile u64 control;
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volatile u64 hpm0;
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volatile u64 hpm1;
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volatile u64 hpm2;
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volatile u64 hpm3;
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volatile u64 error_status;
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volatile u64 ecc_error;
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volatile u64 cctl_command0;
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volatile u64 cctl_access_line0;
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volatile u64 cctl_command1;
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volatile u64 cctl_access_line1;
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volatile u64 cctl_command2;
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volatile u64 cctl_access_line2;
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volatile u64 cctl_command3;
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volatile u64 cctl_access_line4;
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volatile u64 cctl_status;
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};
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/* Control Register */
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#define L2_ENABLE 0x1
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/* prefetch */
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#define IPREPETCH_OFF 3
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#define DPREPETCH_OFF 5
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#define IPREPETCH_MSK (3 << IPREPETCH_OFF)
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#define DPREPETCH_MSK (3 << DPREPETCH_OFF)
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/* tag ram */
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#define TRAMOCTL_OFF 8
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#define TRAMICTL_OFF 10
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#define TRAMOCTL_MSK (3 << TRAMOCTL_OFF)
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#define TRAMICTL_MSK BIT(TRAMICTL_OFF)
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/* data ram */
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#define DRAMOCTL_OFF 11
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#define DRAMICTL_OFF 13
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#define DRAMOCTL_MSK (3 << DRAMOCTL_OFF)
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#define DRAMICTL_MSK BIT(DRAMICTL_OFF)
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/* CCTL Command Register */
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#define CCTL_CMD_REG(base, hart) ((ulong)(base) + 0x40 + (hart) * 0x10)
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#define L2_WBINVAL_ALL 0x12
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/* CCTL Status Register */
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#define CCTL_STATUS_MSK(hart) (0xf << ((hart) * 4))
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#define CCTL_STATUS_IDLE(hart) (0 << ((hart) * 4))
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#define CCTL_STATUS_PROCESS(hart) (1 << ((hart) * 4))
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#define CCTL_STATUS_ILLEGAL(hart) (2 << ((hart) * 4))
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DECLARE_GLOBAL_DATA_PTR;
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struct v5l2_plat {
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struct l2cache *regs;
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u32 iprefetch;
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u32 dprefetch;
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u32 tram_ctl[2];
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u32 dram_ctl[2];
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};
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static int v5l2_enable(struct udevice *dev)
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{
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struct v5l2_plat *plat = dev_get_platdata(dev);
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volatile struct l2cache *regs = plat->regs;
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if (regs)
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setbits_le32(®s->control, L2_ENABLE);
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return 0;
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}
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static int v5l2_disable(struct udevice *dev)
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{
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struct v5l2_plat *plat = dev_get_platdata(dev);
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volatile struct l2cache *regs = plat->regs;
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u8 hart = gd->arch.boot_hart;
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void __iomem *cctlcmd = (void __iomem *)CCTL_CMD_REG(regs, hart);
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if ((regs) && (readl(®s->control) & L2_ENABLE)) {
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writel(L2_WBINVAL_ALL, cctlcmd);
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while ((readl(®s->cctl_status) & CCTL_STATUS_MSK(hart))) {
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if ((readl(®s->cctl_status) & CCTL_STATUS_ILLEGAL(hart))) {
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printf("L2 flush illegal! hanging...");
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hang();
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}
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}
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clrbits_le32(®s->control, L2_ENABLE);
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}
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return 0;
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}
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static int v5l2_ofdata_to_platdata(struct udevice *dev)
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{
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struct v5l2_plat *plat = dev_get_platdata(dev);
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struct l2cache *regs;
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regs = (struct l2cache *)dev_read_addr(dev);
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plat->regs = regs;
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plat->iprefetch = -EINVAL;
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plat->dprefetch = -EINVAL;
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plat->tram_ctl[0] = -EINVAL;
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plat->dram_ctl[0] = -EINVAL;
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/* Instruction and data fetch prefetch depth */
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dev_read_u32(dev, "andes,inst-prefetch", &plat->iprefetch);
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dev_read_u32(dev, "andes,data-prefetch", &plat->dprefetch);
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/* Set tag RAM and data RAM setup and output cycle */
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dev_read_u32_array(dev, "andes,tag-ram-ctl", plat->tram_ctl, 2);
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dev_read_u32_array(dev, "andes,data-ram-ctl", plat->dram_ctl, 2);
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return 0;
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}
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static int v5l2_probe(struct udevice *dev)
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{
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struct v5l2_plat *plat = dev_get_platdata(dev);
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struct l2cache *regs = plat->regs;
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u32 ctl_val;
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ctl_val = readl(®s->control);
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if (!(ctl_val & L2_ENABLE))
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ctl_val |= L2_ENABLE;
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if (plat->iprefetch != -EINVAL) {
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ctl_val &= ~(IPREPETCH_MSK);
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ctl_val |= (plat->iprefetch << IPREPETCH_OFF);
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}
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if (plat->dprefetch != -EINVAL) {
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ctl_val &= ~(DPREPETCH_MSK);
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ctl_val |= (plat->dprefetch << DPREPETCH_OFF);
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}
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if (plat->tram_ctl[0] != -EINVAL) {
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ctl_val &= ~(TRAMOCTL_MSK | TRAMICTL_MSK);
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ctl_val |= plat->tram_ctl[0] << TRAMOCTL_OFF;
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ctl_val |= plat->tram_ctl[1] << TRAMICTL_OFF;
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}
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if (plat->dram_ctl[0] != -EINVAL) {
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ctl_val &= ~(DRAMOCTL_MSK | DRAMICTL_MSK);
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ctl_val |= plat->dram_ctl[0] << DRAMOCTL_OFF;
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ctl_val |= plat->dram_ctl[1] << DRAMICTL_OFF;
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}
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writel(ctl_val, ®s->control);
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return 0;
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}
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static const struct udevice_id v5l2_cache_ids[] = {
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{ .compatible = "v5l2cache" },
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{}
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};
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static const struct cache_ops v5l2_cache_ops = {
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.enable = v5l2_enable,
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.disable = v5l2_disable,
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};
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U_BOOT_DRIVER(v5l2_cache) = {
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.name = "v5l2_cache",
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.id = UCLASS_CACHE,
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.of_match = v5l2_cache_ids,
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.ofdata_to_platdata = v5l2_ofdata_to_platdata,
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.probe = v5l2_probe,
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.platdata_auto_alloc_size = sizeof(struct v5l2_plat),
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.ops = &v5l2_cache_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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