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![Abel Vesa](/assets/img/avatar_default.png)
Update all the dts[i] files for imx6[q|qp|dl] sabre[auto|sd] to the ones from kernel v4.20 (commit 8fe28cb58bcb2). Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
56 lines
1.3 KiB
Plaintext
56 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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//
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// Copyright 2016 Freescale Semiconductor, Inc.
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/dts-v1/;
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#include "imx6qp.dtsi"
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#include "imx6qdl-sabresd.dtsi"
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/ {
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model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board";
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compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp";
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};
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®_arm {
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vin-supply = <&sw2_reg>;
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};
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&iomuxc {
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imx6qdl-sabresd {
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
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MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071
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MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
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MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
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MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
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MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
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MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
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MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
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MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
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MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
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MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071
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MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
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MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
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MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
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MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
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MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
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MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
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MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
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MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
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>;
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};
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};
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};
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&pcie {
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status = "disabled";
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};
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