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https://github.com/brain-hackers/u-boot-brain
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a1f24875c3
The platform-Level Machine Timer (PLMT) block holds memory-mapped mtime register associated with timer tick. This driver implements the riscv_get_time() which is required by the generic RISC-V timer driver. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
54 lines
1.1 KiB
C
54 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019, Rick Chen <rick@andestech.com>
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*
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* U-Boot syscon driver for Andes's Platform Level Machine Timer (PLMT).
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* The PLMT block holds memory-mapped mtime register
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* associated with timer tick.
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*/
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#include <common.h>
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#include <dm.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/syscon.h>
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/* mtime register */
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#define MTIME_REG(base) ((ulong)(base))
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DECLARE_GLOBAL_DATA_PTR;
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#define PLMT_BASE_GET(void) \
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do { \
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long *ret; \
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\
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if (!gd->arch.plmt) { \
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ret = syscon_get_first_range(RISCV_SYSCON_PLMT); \
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if (IS_ERR(ret)) \
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return PTR_ERR(ret); \
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gd->arch.plmt = ret; \
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} \
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} while (0)
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int riscv_get_time(u64 *time)
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{
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PLMT_BASE_GET();
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*time = readq((void __iomem *)MTIME_REG(gd->arch.plmt));
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return 0;
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}
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static const struct udevice_id andes_plmt_ids[] = {
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{ .compatible = "riscv,plmt0", .data = RISCV_SYSCON_PLMT },
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{ }
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};
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U_BOOT_DRIVER(andes_plmt) = {
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.name = "andes_plmt",
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.id = UCLASS_SYSCON,
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.of_match = andes_plmt_ids,
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.flags = DM_FLAG_PRE_RELOC,
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};
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